ser1.c

TDK 6521 SOC 芯片 DEMO程序

/***************************************************************************
 * This code and information is provided "as is" without warranty of any   *
 * kind, either expressed or implied, including but not limited to the     *
 * implied warranties of merchantability and/or fitness for a particular   *
 * purpose.                                                                *
 *                                                                         *
 * Copyright (C) 2005 Teridian Semiconductor Corp. All Rights Reserved.    *
 ***************************************************************************/
//**************************************************************************
//    
//  DESCRIPTION: 71M651x POWER METER - hardware abstraction layer
//  for SERIAL Ports.  The idea here is to hide the hardware just
//  enough that several identical files can include this file
//  and become adapted to a serial port.
// 
//  AUTHOR:  RGV
//
//  HISTORY: See end of file
//
//**************************************************************************
// File: SER1.C
//               
//**************************************************************************
//  Hardware access layer for UART 1
//
#ifndef SER1_C
#define SER1_C 1

#include "options.h"
#if SERIAL1
#include "batmodes.h"
#include "ser1.h"

#if PARITY_NONE_1
#else
bool ser1_error;  // status for the serial port; needed only with parity
#endif

// Get data from the receive register
#pragma save
#pragma NOAREGS
uint8_t ser1_rcv(void) small reentrant
{
    // The RI bit is cleared here to be like other UARTs, where
    // reading the data register clears the ready bit.
    // This lets polling reads always wait for RI,
    // and the applications' interrupt code will always clear RI.
    S1CON &= ~RI_;                    // data is being received
#if PARITY_NONE_1
#if SEVEN_BIT_1
    // 7 bit, no parity
    return (0x7f & S1BUF);
#else
    // 8 bit, no parity
    return S1BUF;
#endif
#else // parity cases
#if SEVEN_BIT_1 
    // 7 bit, parity
    A = S1BUF;                   // Calculate parity, result in flag.
    if (P != PARITY_ODD_1)
        ser1_error = TRUE;          
    return (A & 0x7F);
#else
    // 8 bit, parity
    A = S1BUF;                   // Calculate parity, result in flag.
    if ((((S1CON & RB8_) != 0) ^ P) != PARITY_ODD_1)
        ser1_error = TRUE;          
    return A;
#endif
#endif
}
#pragma restore

// serial interrupts for UART 0
#pragma save
#pragma REGISTERBANK (ES1_BANK)
void es1_isr   (void) small reentrant interrupt ES1_IV using ES1_BANK
{
    if (S1CON & RI_)
    {
       #ifdef SER1_RCV_INT
       // call the higher-level protocol, if any, defined in options.h
       // or main\opt_gbl.h
       SER1_RCV_INT ();
       #else
       ser_rcv();      // no higher protocol- throw away the character
       #endif
    }
    if (S1CON & TI_)
    {
       #ifdef SER1_XMIT_INT
       // call the higher-level protocol, if any, defined in options.h
       // or main\opt_gbl.h
       SER1_XMIT_INT ();
       #else
       ser_disable_xmit_rdy();  // no higher protocol- stop sending
       #endif
    }
}
#pragma restore

// Initialize UART 1
#pragma save
#pragma NOAREGS
void ser1_initialize (enum SERIAL_SPD speed) small reentrant
{
    IEN2 = FALSE;        // Begin critical code section, interrupts OFF.

    S1CON &= ~REN_;      // Make sure it gets reset.


    #if BROWNOUT_BATMODE
    if (batmode_is_brownout())
    {
        S1RELH = BPS_BROWNOUT_300 >> 8;
        S1RELL = BPS_BROWNOUT_300 & 0xFF;
    }
    else
    {
	#endif
        speed += CONFIG0 & MPU_DIV;
        S1RELH = bit_rate_tbl[ speed ] >> 8;
        S1RELL = bit_rate_tbl[ speed ] & 0xFF;
	#if BROWNOUT_BATMODE
    }
	#endif

    #if (((SEVEN_BIT_1 || PARITY_NONE_1) && !STOP_BIT2_1) \
        || (SEVEN_BIT_1 && PARITY_NONE_1 && STOP_BIT2_1))
       // 8N1, 7E1, 7E2, 7N2 are 8 bits; 7N1 is impossible
       // Serial port mode 1, (8-Bit UART), REN, TB8.
       S1CON = _8BIT_SERIAL1_ | REN_ | TB8_;
    #else
       // 8N2, 7E2, 7O2, 8E1, 8O1 are 9 bits; 8E2 and 8O2 are impossible
       // Serial port mode 1, (9-Bit UART), REN, TB8.
       S1CON = _9BIT_SERIAL1_ | REN_ | TB8_;
	#endif

    // When transmit interrupts are enabled, transfer will begin immediately
    // Polling transmits can always check TI first
    S1CON |= TI_;  // transmit is ready

    // clear out unwanted data
    while (ser_rcv_rdy ())
        ser_rcv ();

    #ifdef ser1_error
    ser1_error = FALSE;
    #endif

    // Interrupt priorities are set in main.

    // leave interrupts disabled- enabling interrupts is for application
}
#pragma restore

#endif
#endif
/***************************************************************************
 * $Log: ser1.c,v $
 * Revision 1.23  2006/09/27 00:57:01  tvander
 * More comments
 *
 * Revision 1.22  2006/09/20 23:49:34  tvander
 * Set interrupt priorities only once, during start-up
 *
 * Revision 1.21  2006/09/18 19:22:43  tvander
 * Sets interrupt priorities.
 *
 * Revision 1.20  2006/09/09 01:10:02  gmikef
 * *** empty log message ***
 *
 * Revision 1.19  2006/08/09 00:56:36  tvander
 * *** empty log message ***
 *
 * Revision 1.18  2006/07/18 23:35:51  tvander
 * Wrong register space for initialization routine.
 *
 * Revision 1.17  2006/07/07 00:56:05  tvander
 * Fixed register accesses and baud rate selection.
 *
 * Revision 1.16  2006/03/08 00:00:57  tvander
 * Revised IO so that multiplexed interrupts are centralized in io65xx.c
 * Added default interrupts to io65xx.c
 * Clean build.
 * Tested CE, serial.
 * interrupting EEPROM driver fails.
 *
 * Revision 1.15  2006/03/06 03:32:15  Michael T. Fischer
 * More 6530 prep.
 *
 * Revision 1.13  2005/10/18 02:17:09  tvander
 * Access CLI in brownout by pressing reset.
 * Debugged serial 1 usage from CLI.
 * Implemented scrolling display as M17
 *
 * Revision 1.12  2005/09/22 23:45:07  tvander
 * Clean build all models and unit tests, updated copyright to be fore Teridian
 *
 * Revision 1.11  2005/09/11 00:33:59  tvander
 * Clean compiles
 *
 * Revision 1.10  2005/08/28 02:15:30  gmikef
 * *** empty log message ***
 *
 * Revision 1.9  2005/08/20 01:32:46  gmikef
 * *** empty log message ***
 *
 * Revision 1.8  2005/08/19 01:04:40  gmikef
 * *** empty log message ***
 *
 * Revision 1.7  2005/05/19 00:32:06  tvander
 * Made so SERIAL1 must be 1 for code to compile.
 *
 * Revision 1.6  2005/04/21 02:00:42  gmikef
 * *** empty log message ***
 *
 * Revision 1.5  2005/04/09 02:04:26  gmikef
 * *** empty log message ***
 *
 * Revision 1.5  2005/03/31 00:18:22  tvander
 * Minimally unit tested.
 * UART 0 is tested at 9600 BAUD 7 bits even parity, one stop bit.
 * UART 1 is tested at 300 BAUD 7 bits even parity, one stop bit.
 *
 * Revision 1.4  2005/03/24 22:12:51  tvander
 * Misc improvements
 *
 * Revision 1.3  2005/03/24 01:39:00  tvander
 * First successful compile of serial unit test
 *
 * Revision 1.2  2005/03/23 19:19:32  tvander
 * Added untested timer functions.
 * Updated iicdio and iiceep to reflect improvements in 6510 code.
 * ser0 and ser1 updated to provide features for flag.
 *
 * Revision 1.1  2005/03/15 00:32:35  tvander
 * More realistic hardware abstraction layer.
 *
 * Revision 1.1  2005/03/11 22:17:21  tvander
 * Structure
 *
 * Copyright (C) 2005 Teridian Semiconductor Corp. All Rights Reserved.    *
 * this program is fully protected by the United States copyright          *
 * laws and is the property of Teridian Semiconductor Corporation.         *
 ***************************************************************************/