reg80515.h

TDK 6521 SOC 芯片 DEMO程序

#define I3FR_   BIT6    // External 3 interrupt edge.
#define I2FR_   BIT5    // External 2 interrupt edge.
//========================================================================//
// PSW = 0xD0;
sbit CY    = PSW^7;     // Carry flag.
sbit AC    = PSW^6;     // Auxilary carry flag for BCD operations.
sbit F0    = PSW^5;     // General purpose flag.
sbit RS1   = PSW^4;     // RS1:0 Register bank select.
sbit RS0   = PSW^3;     // 
sbit OV    = PSW^2;     // Overflow flag.
sbit F1    = PSW^1;     // General purpose flag.   
sbit P     = PSW^0;     // Parity flag.   (i.e. EVEN parity).

#define CY_     BIT7    // Carry flag.
#define AC_     BIT6    // Auxilary carry flag for BCD operations.
#define F0_     BIT5    // General purpose flag.
#define RS1_    BIT4    // RS1:0 Register bank select.
#define RS0_    BIT3    // 
#define OV_     BIT2    // Overflow flag.
#define F1_     BIT1    // General purpose flag.   
#define P_      BIT0    // Parity flag (i.e. EVEN parity).
//========================================================================//
// WDCON = 0xD8;
sbit ES0_SEL = WDCON^7;  // 1 => Serial 0 clocked by S0REL.
                         // 0 => Serial 0 clocked by TH1 (Timer 1).
#define ES0_SEL_ BIT7

////////////////////////////////////////////////////////////////////////////
// BYTE Special Function Registers.
////////////////////////////////////////////////////////////////////////////
//========================================================================//
// Defines for WDTREL = 0x86;
#define PRESCALE_16_    BIT7    // 16X core watchdog timeout.
#define WDT_RELOAD_     0x7F    // Core watchdog reload value.
//========================================================================//
// Defines for PCON = 0x87;
#define SMOD_           BIT7    // Double baud rate for Serial 0.
#define GF1_            BIT3    // General use flag.
#define GF0_            BIT2    // General use flag.
#define PD_             BIT1    // STOP, power down.
#define IDL_            BIT0    // Idle MPU.
#define PD              1       // Powerdown MPU.
//===========================================================================//
// Defines for TMOD = 0x89;
#define T1_GATE_        BIT7    // Timer 1 is gated via INT1.
#define T1_CNTR_        BIT6    // Timer 1 is a counter.
#define T1_TMR_         NO_BITS // Timer 1 is a timer.
#define T1_13_          NO_BITS // Timer 1 is a 13-bit counter/timer.
#define T1_08_          BIT5    // Timer 1 is a 8-bit auto-reload counter/timer.
#define T1_16_          BIT4    // Timer 1 is a 16-bit counter/timer.
#define T1_STOP_        0x30    // Timer 1 is a stopped.

#define T0_GATE_        BIT3    // Timer 0 is gated via INT0.
#define T0_CNTR_        BIT2    // Timer 0 is a counter.
#define T0_TMR_         NO_BITS // Timer 0 is a timer.
#define T0_13_          NO_BITS // Timer 0 is a 13-bit counter/timer.
#define T0_08_          BIT1    // Timer 0 is a 8-bit auto-reload counter/timer.
#define T0_16_          BIT0    // Timer 0 is a 16-bit counter/timer.
#define T0_08_2_        0x03    // Timer 0 is a dual 8-bit counters/timers.
//===========================================================================//
// Defines for CKCON = 0x8E;
#define WAIT_           0x70    // Wait states between instruction fetches.
#define WAIT_0_         0x00    // Default value.
#define WAIT_1_         0x10
#define WAIT_2_         0x20
#define WAIT_3_         0x30
#define WAIT_4_         0x40
#define WAIT_5_         0x50
#define WAIT_6_         0x60
#define WAIT_7_         0x70

#define STRETCH_        0x07    // Wait states between XRAM reads or writes.
#define STRETCH_0_      0x00
#define STRETCH_1_      0x01    // Default value.
#define STRETCH_2_      0x02
#define STRETCH_3_      0x03
#define STRETCH_4_      0x04
#define STRETCH_5_      0x05
#define STRETCH_6_      0x06 // Use when reading MSB or writing LSB of CE data.
#define STRETCH_7_      0x07
//===========================================================================//
// Defines for DPS = 0x92;
#define DPS1_           BIT7    // Select DPTR1.
//===========================================================================//
// Defines for IEN2 = 0x9A;
#define ES1_            BIT0    // Enable/Disable SERIAL1 interrupts.
//===========================================================================//
// Together w/ IPH allows four priority levels for six groups of interrupts.
// Defines for IPL = 0xA9;  
#define OWDS_           BIT7    //
#define WDTS_           BIT6    // Core watchdog timer status.
#define PX6_L_          BIT5    // EX6      priority LSb.
#define PX5S0_L_        BIT4    // EX5/ES0  priority LSb.
#define PX4T1_L_        BIT3    // EX4/TMR1 priority LSb.
#define PX3X1_L_        BIT2    // EX3/EX1  priority LSb.
#define PX2T0_L_        BIT1    // EX2/TMR0 priority LSb.
#define PX0S1_L_        BIT0    // EX0/ES1  priority LSb.
//===========================================================================//
// Defines for IPH = 0xB9;
#define PX6_H_          BIT5    // EX6      priority MSb.
#define PX5S0_H_        BIT4    // EX5/ES0  priority MSb.
#define PX4T1_H_        BIT3    // EX4/TMR1 priority MSb.
#define PX3X1_H_        BIT2    // EX3/EX1  priority MSb.
#define PX2T0_H_        BIT1    // EX2/TMR0 priority MSb.
#define PX0S1_H_        BIT0    // EX0/ES1  priority MSb.
#define IP_MSK          0x3F    // Interrupt Priority Mask.
//===========================================================================//
sfr ADRMSB = 0xBF;              // MSB of MOVX @Ri instructions.

// Generic SFR definitions.
sfr DPL  = 0x82;       // Data Pointer Low.
sfr DPH  = 0x83;       // Data Pointer High.
sfr SCON = 0x98;       // Serial Port, Control Register.
sfr SBUF = 0x99;       // Serial Port, Data Buffer.
sfr IE   = 0xA8;       // Interrupt Enable Register.
sfr IP   = 0xA9;       // Interrupt Priority Register.

sfr IPL	 = 0xA9;	   // Low-order Interrupt Priority Register.
sfr IPH	 = 0xB9;	   // High-order Interrupt Priority Register.

// Interrupt Vector Address = IV * 8 + 3.
#define EX0_IV 		 0
#define TMR0_IV		 1
#define EX1_IV 		 2
#define TMR1_IV		 3
#define ES0_IV 		 4
#define EX2_IV 		 9
#define EX3_IV 		10
#define EX4_IV 		11
#define EX5_IV 		12
#define EX6_IV 		13
#define ES1_IV 		16

/***************************************************************************
 * History:
 * $Log: reg80515.h,v $
 * Revision 1.9  2006/09/09 01:15:51  gmikef
 * *** empty log message ***
 *
 * Revision 1.7  2005/09/22 23:45:28  tvander
 * Clean build all models and unit tests, updated copyright to be fore Teridian
 *
 * Revision 1.6  2005/04/30 02:20:25  gmikef
 * *** empty log message ***
 *
 * Revision 1.5  2005/04/28 19:12:28  tvander
 * Comments only!  Restored history comments.
 *
 * Revision 1.4  2005/04/27 23:48:52  gmikef
 * Some MATH rountines now use 'idata'.
 * Added MATH_FAST flag to 'options.h".
 * Changed "6521B.Uv2" to max optimization.
 *
 * Revision 1.3  2005/04/21 02:08:55  gmikef
 * *** empty log message ***
 *
 * Revision 1.2  2005/04/06 18:10:12  gmikef
 * *** empty log message ***
 *
 * Revision 1.1  2005/03/24 21:45:47  gmikef
 * *** empty log message ***
 *
 * Copyright (C) 2005 Teridian Semiconductor Corp. All Rights Reserved.    *
 * this program is fully protected by the United States copyright          *
 * laws and is the property of Teridian Semiconductor Corporation.         *
 ***************************************************************************/
#endif  /* reg80515.h */