reg80515.h

TDK 6521 SOC 芯片 DEMO程序

/***************************************************************************
 * This code and information is provided "as is" without warranty of any   *
 * kind, either expressed or implied, including but not limited to the     *
 * implied warranties of merchantability and/or fitness for a particular   *
 * purpose.                                                                *
 *                                                                         *
 * Copyright (C) 2005 Teridian Semiconductor Corp. All Rights Reserved.    *
 ***************************************************************************/
//**************************************************************************
//    
//  DESCRIPTION: 71M651x POWER METER - 80515 Special Function Registers.
// 
//  AUTHOR:  MTF
//
//  HISTORY: See end of file
//
//**************************************************************************
//               
// File: REG80515.H
//               
#ifndef _REG80515
#define _REG80515

//==Bit-addressable Registers=============================================//
sfr P0    = 0x80;       // Port 0.
sfr TCON  = 0x88;       // Timer/Counter Control.
sfr P1    = 0x90;       // Port 1.
sfr S0CON = 0x98;       // Serial Port 0, Control Register.
sfr P2    = 0xA0;       // Port 2.
sfr IEN0  = 0xA8;       // Interrupt Enable Register 0.
sfr P3    = 0xB0;       // Port 3.
sfr IEN1  = 0xB8;       // Interrupt Enable Register 1.
sfr IRCON = 0xC0;       // Interrupt Request Control Register.
sfr T2CON = 0xC8;       // External interrupt 2/3 edge.
sfr PSW   = 0xD0;       // Program Status Word.
sfr WDCON = 0xD8;       // Power Fail Control Register.
sfr ACC   = 0xE0;       // Accumulator.
sfr B     = 0xF0;       // B-register.

//==BYTE Registers========================================================//
sfr SP    = 0x81;       // Stack Pointer.
sfr DPL0  = 0x82;       // Data Pointer Low  0.
sfr DPH0  = 0x83;       // Data Pointer High 0.
sfr DPL1  = 0x84;       // Data Pointer Low  1.
sfr DPH1  = 0x85;       // Data Pointer High 1.
sfr WDTREL = 0x86;      // Watchdog timer reload.
sfr PCON  = 0x87;       // Power Control.

sfr TMOD  = 0x89;       // Timer Mode Control.
sfr TL0   = 0x8A;       // Timer 0, low byte.
sfr TL1   = 0x8B;       // Timer 1, low byte.
sfr TH0   = 0x8C;       // Timer 0, high byte.
sfr TH1   = 0x8D;       // Timer 1, high byte.
sfr CKCON = 0x8E;       // Clock Control (Default: Wait = 0, Stretch = 1).

sfr DPS   = 0x92;       // DPTR select.

sfr S0BUF  = 0x99;      // Serial Port 0, Data Buffer.
sfr IEN2   = 0x9A;      // Interrupt Enable Register 2.
sfr S1CON  = 0x9B;      // Serial Port 1, Control Register.
sfr S1BUF  = 0x9C;      // Serial Port 1, Data Buffer.
sfr S1RELL = 0x9D;      // Serial Port 1, Reload Register, low byte.

sfr IP0    = 0xA9;      // Interrupt Priority Register 0.
sfr S0RELL = 0xAA;      // Serial Port 0, Reload Register, low byte.

sfr IP1    = 0xB9;      // Interrupt Priority Register 1.
sfr S0RELH = 0xBA;      // Serial Port 0, Reload Register, high byte.
sfr S1RELH = 0xBB;      // Serial Port 1, Reload Register, high byte.

////////////////////////////////////////////////////////////////////////////
// BIT Special Function Registers.
////////////////////////////////////////////////////////////////////////////

//========================================================================//
// TCON = 0x88;
sbit TF1   = TCON^7;    // Timer 1 overflow.
sbit TR1   = TCON^6;    // Timer 1 run.
sbit TF0   = TCON^5;    // Timer 0 overflow. 
sbit TR0   = TCON^4;    // Timer 0 run. 
sbit IE1   = TCON^3;    // Interrupt 1 occurred (Auto-cleared).
sbit IT1   = TCON^2;    // Interrupt 1 on falling edge /low-level.
sbit IE0   = TCON^1;    // Interrupt 0 occurred (Auto-cleared).
sbit IT0   = TCON^0;    // Interrupt 0 on falling edge /low-level.

#define   TF1_  BIT7    // Timer 1 overflow.
#define   TR1_  BIT6    // Timer 1 run.
#define   TF0_  BIT5    // Timer 0 overflow. 
#define   TR0_  BIT4    // Timer 0 run. 
#define   IE1_  BIT3    // Interrupt 1 occurred (Auto-cleared).
#define   IT1_  BIT2    // Interrupt 1 on falling edge /low-level.
#define   IE0_  BIT1    // Interrupt 0 occurred (Auto-cleared).
#define   IT0_  BIT0    // Interrupt 0 on falling edge /low-level.
//========================================================================//
// S0CON = 0x98 (aka SCON).
sbit SM0   = S0CON^7;   // Mode bits.
sbit SM1   = S0CON^6;   //
sbit SM2   = S0CON^5;   //
sbit REN   = S0CON^4;   // Enable receiver.
sbit TB8   = S0CON^3;   // BIT8 xmt'd.
sbit RB8   = S0CON^2;   // BIT8 rcv'd.
sbit TI    = S0CON^1;   // TXD interrupt'd.
sbit RI    = S0CON^0;   // RXD interrupt'd.

#define   SM0_   BIT7   // Defines for S0CON = 0x98 & S1CON = 0x9B except SM_;
#define   SM1_   BIT6
#define   SM2_   BIT5
#define   REN_   BIT4   // Enable receiver. 
#define   TB8_   BIT3   // BIT8 xmt'd.
#define   RB8_   BIT2   // BIT8 rcv'd.
#define   TI_    BIT1   // TXD interrupt.
#define   RI_    BIT0   // RXD interrupt.
                        // Defines for S0CON = 0x98 exclusively;
#define _8BIT_SERIAL0_    0|SM1_
#define _9BIT_SERIAL0_ SM0_|SM1_

#define SM_ BIT7        // Defines for S1CON = 0x9B exclusively;
#define _8BIT_SERIAL1_ SM_
#define _9BIT_SERIAL1_  0
//========================================================================//
// IEN0 = 0xA8; (aka IE).
sbit EA    = IEN0^7;    // Enable/Disable ALL interrupts.
sbit WDT   = IEN0^6;    // Watchdog timer refresh.
sbit ES0   = IEN0^4;    // Enable Serial 0 interrupts.
sbit ET1   = IEN0^3;    // Enable Timer 1 interrupts.
sbit EX1   = IEN0^2;    // Enable External 1 interrupts.
sbit ET0   = IEN0^1;    // Enable Timer 0 interrupts.
sbit EX0   = IEN0^0;    // Enable External 0 interrupts.

#define EA_     BIT7    // Enable/Disable ALL interrupts.
#define WDT_    BIT6    // Watchdog timer refresh.
#define ES0_    BIT4    // Enable Serial 0 interrupts.
#define ET1_    BIT3    // Enable Timer 1 interrupts.
#define EX1_    BIT2    // Enable External 1 interrupts.
#define ET0_    BIT1    // Enable Timer 0 interrupts.
#define EX0_    BIT0    // Enable External 0 interrupts.
//========================================================================//
// IEN1 = 0xB8;
sbit SWDT  = IEN1^6;    // Watchdog timer start/refresh.
sbit EX6   = IEN1^5;    // Enable External 6 interrupts.
sbit EX5   = IEN1^4;    // Enable External 5 interrupts.
sbit EX4   = IEN1^3;    // Enable External 4 interrupts.
sbit EX3   = IEN1^2;    // Enable External 3 interrupts.
sbit EX2   = IEN1^1;    // Enable External 2 interrupts.

#define SWDT_   BIT6    // Watchdog timer start/refresh.
#define EX6_    BIT5    // Enable External 6 interrupts.
#define EX5_    BIT4    // Enable External 5 interrupts.
#define EX4_    BIT3    // Enable External 4 interrupts.
#define EX3_    BIT2    // Enable External 3 interrupts.
#define EX2_    BIT1    // Enable External 2 interrupts.
//========================================================================//
// IRCON = 0xC0;
sbit IE6 = IRCON^5;     // External interrupt 6 (Auto-cleared).
sbit IE5 = IRCON^4;     // External interrupt 5 (Auto-cleared).
sbit IE4 = IRCON^3;     // External interrupt 4 (Auto-cleared).
sbit IE3 = IRCON^2;     // External interrupt 3 (Auto-cleared).
sbit IE2 = IRCON^1;     // External interrupt 2 (Auto-cleared).

#define IE6_    BIT5    // External interrupt 6 (Auto-cleared).
#define IE5_    BIT4    // External interrupt 5 (Auto-cleared).
#define IE4_    BIT3    // External interrupt 4 (Auto-cleared).
#define IE3_    BIT2    // External interrupt 3 (Auto-cleared).
#define IE2_    BIT1    // External interrupt 2 (Auto-cleared).
//========================================================================//
// T2CON = 0xC8;        // 0 => falling edge, 1 => rising edge.
sbit I3FR   = T2CON^6;  // External 3 interrupt edge.
sbit I2FR   = T2CON^5;  // External 2 interrupt edge.