dm642gel.txt

dsp dm642 flash烧录入

setup_memory_map()
{
    GEL_MapOn();
    GEL_MapReset();

 
    /* Off-chip memory map */
    GEL_MapAdd(0x80000000, 0, 0x02000000, 1, 1); /* 32MB SDRAM EMIF-A, CE0*/
    GEL_MapAdd(0xA0000000, 0, 0x10000000, 1, 1); /* EMIF-A, CE2 EXPANSION */
    GEL_MapAdd(0xB0000000, 0, 0x10000000, 1, 1); /* EMIF-A, CE3 EXPANSION */
}

/*--------------------------------------------------------------*/
/* init_emif()                                                  */
/*--------------------------------------------------------------*/
init_emif()
{
    #define EMIFA_GCTL       0x01800000
    #define EMIFA_CE1        0x01800004
    #define EMIFA_CE0        0x01800008
    #define EMIFA_CE2        0x01800010
    #define EMIFA_CE3        0x01800014
    #define EMIFA_SDRAMCTL   0x01800018
    #define EMIFA_SDRAMTIM   0x0180001c
    #define EMIFA_SDRAMEXT   0x01800020
    #define EMIFA_CE1SECCTL  0x01800044
    #define EMIFA_CE0SECCTL  0x01800048
    #define EMIFA_CE2SECCTL  0x01800050
    #define EMIFA_CE3SECCTL  0x01800054

    /* EMIFA */
    *(int *)EMIFA_GCTL     = 0x00052078;
    *(int *)EMIFA_CE0      = 0xffffffd3;  /* CE0 SDRAM                     */
    *(int *)EMIFA_SDRAMCTL = 0x57115000;  /* SDRAM control                 */
    *(int *)EMIFA_SDRAMTIM = 0x0000081b;  /* SDRAM timing (refresh)        */
    *(int *)EMIFA_SDRAMEXT = 0x001faf4d;  /* SDRAM extended control        */
    *(int *)EMIFA_CE0SECCTL= 0x00000002;  /* CE0 Secondary Control Reg.    */
    *(int *)EMIFA_CE1SECCTL= 0x00000002;  /* CE1 Secondary Control Reg.    */
    *(int *)EMIFA_CE2SECCTL= 0x00000002;  /* CE2 Secondary Control Reg.    */
    *(int *)EMIFA_CE3SECCTL= 0x00000073;  /* CE3 Secondary Control Reg.    */
}