atom_define.h

dsp dm642 flash烧录入

/*

  typedef unsigned char    Uint8;
  typedef unsigned short   Uint16;
  typedef unsigned int     Uint32;
  typedef unsigned long    Uint40;
  typedef char             Int8;
  typedef short            Int16;
  typedef int              Int32;
  typedef long             Int40;
 
  typedef double           Int64;
  */



#define HPIC            0x01880000
#define rest_fifo       0xFF0000                 
#define FIFOWords       64


/******** Device Configeration Register ******/
#define  PERCFG_ADDR         	0x01B3F000    /*  */
#define  PCFGLOCK_ADDR         	0x01B3F018    /*  */
#define  PERCFG      (*(volatile unsigned int *)PERCFG_ADDR)
#define  PCFGLOCK     (*(volatile unsigned int *)PCFGLOCK_ADDR)
/************EMIFA Register Addr*******************************************/

#define  EMIFA_GBLCTL_ADDR         0x01800000    /*EMIF global control register  */
#define  EMIFA_CE1CTL_ADDR         0x01800004    /*EMIF CE1 space control register*/
#define  EMIFA_CE0CTL_ADDR         0x01800008    /*EMIF CE0 space control register*/
#define  EMIFA_CE2CTL_ADDR         0x01800010    /*EMIF CE2 space control register*/
#define  EMIFA_CE3CTL_ADDR         0x01800014    /*EMIF CE3 space control register*/

#define  EMIFA_CE1SEC_ADDR         0x01800044    /*EMIF CE1 space control register*/
#define  EMIFA_CE0SEC_ADDR         0x01800048    /*EMIF CE0 space control register*/
#define  EMIFA_CE2SEC_ADDR         0x01800050    /*EMIF CE2 space control register*/
#define  EMIFA_CE3SEC_ADDR         0x01800054    /*EMIF CE3 space control register*/

#define  EMIFA_SDCTL_ADDR          0x01800018    /*EMIF SDRAM control register    */
#define  EMIFA_SDTIM_ADDR          0x0180001c    /*EMIF SDRAM refresh control     */
#define  EMIFA_SDEXT_ADDR          0x01800020    /*EMIF SDRAM extend register     */

#define EMIFA_GBLCTL      (*(volatile unsigned int *)EMIFA_GBLCTL_ADDR)
#define EMIFA_CE0CTL      (*(volatile unsigned int *)EMIFA_CE0CTL_ADDR)
#define EMIFA_CE1CTL      (*(volatile unsigned int *)EMIFA_CE1CTL_ADDR)
#define EMIFA_CE2CTL      (*(volatile unsigned int *)EMIFA_CE2CTL_ADDR)
#define EMIFA_CE3CTL      (*(volatile unsigned int *)EMIFA_CE3CTL_ADDR)

#define EMIFA_CE0SEC      (*(volatile unsigned int *)EMIFA_CE0SEC_ADDR)
#define EMIFA_CE1SEC      (*(volatile unsigned int *)EMIFA_CE1SEC_ADDR)
#define EMIFA_CE2SEC      (*(volatile unsigned int *)EMIFA_CE2SEC_ADDR)
#define EMIFA_CE3SEC      (*(volatile unsigned int *)EMIFA_CE3SEC_ADDR)

#define EMIFA_SDCTL      (*(volatile unsigned int *)EMIFA_SDCTL_ADDR)
#define EMIFA_SDTIM      (*(volatile unsigned int *)EMIFA_SDTIM_ADDR)
#define EMIFA_SDEXT      (*(volatile unsigned int *)EMIFA_SDEXT_ADDR)

/*************interrupt Register addr*******************/
#define MUXH_ADDR	             0x019c0000
#define MUXL_ADDR	             0x019c0004
#define EXTPOL_ADDR	             0x019c0000
#define MUXH               *(volatile unsigned int *)(MUXH_ADDR)
#define MUXL               *(volatile unsigned int *)(MUXL_ADDR)
#define EXTPOL             *(volatile unsigned int *)(EXTPOL_ADDR)



/**************PCI Register Addr********************************************/
#define PCI_RSTSRC_ADDR		 0x01C00000
#define PCI_PMDCSR_ADDR		 0x01C00004
#define PCI_PCIIS_ADDR		 0x01C00008
#define PCI_PCIIEN_ADDR		 0x01C0000c
#define PCI_DSPMA_ADDR		 0x01C00010
#define PCI_PCIMA_ADDR		 0x01C00014
#define PCI_PCIMC_ADDR		 0x01C00018
#define PCI_CDSPA_ADDR		 0x01C0001c
#define PCI_CPCIA_ADDR		 0x01C00020
#define PCI_CCNT_ADDR		 0x01C00024
#define PCI_HALT_ADDR		 0x01C00028
#define PCI_EEADD_ADDR		 0x01c20000
#define PCI_EEDAT_ADDR		 0x01c20004
#define PCI_EECTL_ADDR		 0x01c20008

#define PCI_HSR		     *(volatile unsigned int *)(PCI_IO_BASE_ADDR)	
#define PCI_HDCR		 *(volatile unsigned int *)(PCI_IO_BASE_ADDR+4)	
#define PCI_DSPP		 *(volatile unsigned int *)(PCI_IO_BASE_ADDR+8)

#define PCI_RSTSRC		 *(volatile unsigned int *)(PCI_RSTSRC_ADDR)
#define PCI_PMDCSR		 *(volatile unsigned int *)(PCI_PMDCSR_ADDR)
#define PCI_PCIIS		 *(volatile unsigned int *)(PCI_PCIIS_ADDR)
#define PCI_PCIIEN		 *(volatile unsigned int *)(PCI_PCIIEN_ADDR)
#define PCI_DSPMA		 *(volatile unsigned int *)(PCI_DSPMA_ADDR)
#define PCI_PCIMA		 *(volatile unsigned int *)(PCI_PCIMA_ADDR)
#define PCI_PCIMC		 *(volatile unsigned int *)(PCI_PCIMC_ADDR)
#define PCI_CDSPA		 *(volatile unsigned int *)(PCI_CDSPA_ADDR)
#define PCI_CPCIA		 *(volatile unsigned int *)(PCI_CPCIA_ADDR)
#define PCI_CCNT		 *(volatile unsigned int *)(PCI_CCNT_ADDR)
#define PCI_HALT		 *(volatile unsigned int *)(PCI_HALT_ADDR)

#define PCI_EEADD		 *(volatile unsigned int *)(PCI_EEADD_ADDR)
#define PCI_EEDAT		 *(volatile unsigned int *)(PCI_EEDAT_ADDR)
#define PCI_EECTL		 *(volatile unsigned int *)(PCI_EECTL_ADDR)

/**************TIMER Register Addr**************************************/
#define TIME0_CTL_ADDR 0x01940000
#define TIME0_PRD_ADDR 0x01940004
#define TIME0_CNT_ADDR 0x01940008

#define TIME1_CTL_ADDR 0x01980000
#define TIME1_PRD_ADDR 0x01980004
#define TIME1_CNT_ADDR 0x01980008

#define TIME2_CTL_ADDR 0x01AC0000
#define TIME2_PRD_ADDR 0x01AC0004
#define TIME2_CNT_ADDR 0x01AC0008


#define TIME0_CTL      	(*(volatile unsigned int *)TIME0_CTL_ADDR)
#define TIME0_PRD      	(*(volatile unsigned int *)TIME0_PRD_ADDR)
#define TIME0_CNT      	(*(volatile unsigned int *)TIME0_CNT_ADDR)
#define TIME1_CTL      	(*(volatile unsigned int *)TIME1_CTL_ADDR)
#define TIME1_PRD      	(*(volatile unsigned int *)TIME1_PRD_ADDR)
#define TIME1_CNT      	(*(volatile unsigned int *)TIME1_CNT_ADDR)
#define TIME2_CTL      	(*(volatile unsigned int *)TIME2_CTL_ADDR)
#define TIME2_PRD      	(*(volatile unsigned int *)TIME2_PRD_ADDR)
#define TIME2_CNT      	(*(volatile unsigned int *)TIME2_CNT_ADDR)



/**************I2C Register Addr********************************************/
#define I2COAR_ADDR			0x01B40000		/*I2C own address register*/
#define I2CIER_ADDR			0x01B40004		/*I2C interrupt enable register*/
#define I2CSTR_ADDR			0x01B40008		/*I2C status register*/
#define I2CCLKL_ADDR		0x01B4000C		/*I2C clock low-time divider register*/
#define I2CCLKH_ADDR		0x01B40010		/*I2C clock high-time divider register*/
#define I2CCNT_ADDR			0x01B40014		/*I2C data count register*/
#define I2CDRR_ADDR			0x01B40018		/*I2C data receive register*/
#define I2CSAR_ADDR			0x01B4001C		/*I2C slave address register*/
#define I2CDXR_ADDR			0x01B40020		/*I2C data transmit register*/
#define I2CMDR_ADDR			0x01B40024		/*I2C mode register*/
#define I2CISR_ADDR			0x01B40028		/*I2C interrupt source register*/
#define I2CPSC_ADDR			0x01B40030		/*I2C prescaler register*/
 

#define I2COAR      	(*(volatile unsigned int *)I2COAR_ADDR)
#define I2CIER    		(*(volatile unsigned int *)I2CIER_ADDR)
#define I2CSTR  	    (*(volatile unsigned int *)I2CSTR_ADDR)
#define I2CCLKL  	    (*(volatile unsigned int *)I2CCLKL_ADDR)
#define I2CCLKH  	    (*(volatile unsigned int *)I2CCLKH_ADDR)
#define I2CCNT   	    (*(volatile unsigned int *)I2CCNT_ADDR)
#define I2CDRR    		(*(volatile unsigned int *)I2CDRR_ADDR)
#define I2CSAR 		    (*(volatile unsigned int *)I2CSAR_ADDR)
#define I2CMDR  	    (*(volatile unsigned int *)I2CMDR_ADDR)
#define I2CDXR  	    (*(volatile unsigned int *)I2CDXR_ADDR)
#define I2CISR  	    (*(volatile unsigned int *)I2CISR_ADDR)
#define I2CPSC   	    (*(volatile unsigned int *)I2CPSC_ADDR)

/****************Video port1 Addr*************************************************/
#define	VPPID1_ADDR			0x01C44000		/*video port peripheral identification register*/
#define	VPPCR1_ADDR			0x01C44004		/*video port peripheral control register*/
#define	VPPFUNC1_ADDR		0x01C44020		/*video port pin function register*/
#define	VPPDIR1_ADDR		0x01C44024		/*video port pin direction register*/
#define	VPPDIN1_ADDR		0x01C44028		/*video port pin data input register*/

#define	VPPDOUT1_ADDR		0x01C4402C		/*video port pin data output register*/
#define	VPPDSET1_ADDR		0x01C44030		/*video port pin data set register*/
#define	VPPDCLR1_ADDR		0x01C44034		/*video port pin data clear register*/
#define	VPPIEN1_ADDR		0x01C44038		/*video port pin interrupt enable register*/
#define	VPPIPO1_ADDR		0x01C4403C		/*video port pin interrupt polarity register*/

#define VPPISTAT1_ADDR		0x01C44040		/*video port pin interrupt status register*/
#define	VPPICLR1_ADDR		0x01C44044		/*video port pin interrupt clear register*/
#define	VPCTL1_ADDR			0x01C440C0		/*video port control register*/
#define	VPSTAT1_ADDR		0x01C440C4		/*video port status register*/
#define	VPIE1_ADDR			0x01C440C8		/*video port interrupt enable register*/

#define	VPIS1_ADDR			0x01C440CC		/*video port interrupt status register*/
#define	VCASTAT1_ADDR		0x01C44100		/*video capture channel A status register*/
#define	VCACTL1_ADDR		0x01C44104		/*video capture channel A control register*/
#define	VCASTRT11_ADDR		0x01C44108		/*video capture channel A field 1 start register*/
#define	VCASTOP12_ADDR		0x01C4410C		/*video capture channel A field 2 stop register*/

#define	VCASTRT12_ADDR		0x01C44110		/*video capture channel A field 2 start register*/
#define	VCASTOP11_ADDR		0x01C44114		/*video capture channel A field 1 stop register*/
#define	VCAVINT1_ADDR		0x01C44118		/*video capture channel A vertical interrupt register*/
#define	VCATHRLD1_ADDR		0x01C4411C		/*video capture channel A threshold register*/
#define	VCAEVCT1_ADDR		0x01C44120		/*video capture channel A event count register*/

#define Y_SRCA_ADDR			0x78000000		/*Y FIFO source register A*/
#define CB_SRCA_ADDR		0x78000008		/*CB FIFO source register A*/
#define CR_SRCA_ADDR		0x78000010		/*CR FIFO source register A*/


#define VPPID1      	(*(volatile unsigned int *)VPPID1_ADDR)