boot.asm

dsp dm642 flash烧录入

    .ref    _c_int00
    .global RESET_RST
        
FLASH_START   .equ    0x64000400        ;flash start address
CODE_START    .equ    0x00000400        ;start of non boot code
CODE_SIZE     .equ    0x00003000        ;application code size in byte
  

	.sect ".bootload"
	; global EMIF symbols defined for the c671x family
            .include        boot_dm642.h62
_boot_start:
          zero B1
_myloop:  ; [!B1] B _myloop  
            nop  5
_myloopend: nop



   ;************************************************************************
   ;* CONFIGURE EMIF
   ;************************************************************************

        ;****************************************************************
        ; *EMIF_GCTL = EMIF_GCTL_V;
        ;****************************************************************

            mvkl  EMIF_GCTL,A4    
      ||    mvkl  EMIF_GCTL_V,B4

            mvkh  EMIF_GCTL,A4
      ||    mvkh  EMIF_GCTL_V,B4

            stw   B4,*A4

        ;****************************************************************
        ; *EMIF_CE0 = EMIF_CE0_V
        ;****************************************************************

            mvkl  EMIF_CE0,A4       
      ||    mvkl  EMIF_CE0_V,B4     

            mvkh  EMIF_CE0,A4
      ||    mvkh  EMIF_CE0_V,B4

            stw   B4,*A4

        ;****************************************************************
        ; *EMIF_CE1 = EMIF_CE1_V (setup for 8-bit async)
        ;****************************************************************

            mvkl  EMIF_CE1,A4       
      ||    mvkl  EMIF_CE1_V,B4

            mvkh  EMIF_CE1,A4
      ||    mvkh  EMIF_CE1_V,B4

            stw   B4,*A4
        
        ;****************************************************************
        ; *EMIF_CE2 = EMIF_CE2_V (setup for 32-bit async)
        ;****************************************************************

            mvkl  EMIF_CE2,A4       
      ||    mvkl  EMIF_CE2_V,B4

            mvkh  EMIF_CE2,A4
      ||    mvkh  EMIF_CE2_V,B4

            stw   B4,*A4

        ;****************************************************************
        ; *EMIF_CE3 = EMIF_CE3_V (setup for 32-bit async)
        ;****************************************************************

      ||    mvkl  EMIF_CE3,A4    
      ||    mvkl  EMIF_CE3_V,B4     ;

            mvkh  EMIF_CE3,A4
      ||    mvkh  EMIF_CE3_V,B4

            stw   B4,*A4
            
      ;****************************************************************
        ; *EMIF_CE1SEC = EMIF_CE1SEC_V (setup for 8-bit async)
        ;****************************************************************

      ||    mvkl  EMIF_CE1SEC,A4    
      ||    mvkl  EMIF_CE1SEC_V,B4     ;

            mvkh  EMIF_CE1SEC,A4
      ||    mvkh  EMIF_CE1SEC_V,B4

            stw   B4,*A4
             ;****************************************************************
        ; *EMIF_CE0SEC= EMIF_CE0SEC_V (setup for 64-bit async)
        ;****************************************************************

      ||    mvkl  EMIF_CE0SEC,A4    
      ||    mvkl  EMIF_CE0SEC_V,B4     ;

            mvkh  EMIF_CE0SEC,A4
      ||    mvkh  EMIF_CE0SEC_V,B4

            stw   B4,*A4 
       ;****************************************************************
        ; *EMIF_CE2SEC = EMIF_CE2_V 
        ;****************************************************************

      ||    mvkl  EMIF_CE2SEC,A4    
      ||    mvkl  EMIF_CE2SEC_V,B4     ;

            mvkh  EMIF_CE2SEC,A4
      ||    mvkh  EMIF_CE2SEC_V,B4

            stw   B4,*A4
             ;****************************************************************
        ; *EMIF_CE3SEC = EMIF_CE3SEC_V (setup for 16-bit async)
        ;****************************************************************

      ||    mvkl  EMIF_CE3SEC,A4    
      ||    mvkl  EMIF_CE3SEC_V,B4     ;

            mvkh  EMIF_CE3SEC,A4
      ||    mvkh  EMIF_CE3SEC_V,B4

            stw   B4,*A4

        ;****************************************************************
        ; *EMIF_SDRAMCTL = EMIF_SDRAMCTL_V
        ;****************************************************************
      ||    mvkl  EMIF_SDRAMCTL,A4      
      ||    mvkl  EMIF_SDRAMCTL_V,B4    ;

            mvkh  EMIF_SDRAMCTL,A4
      ||    mvkh  EMIF_SDRAMCTL_V,B4

            stw   B4,*A4

        ;****************************************************************
        ; *EMIF_SDRAMTIM = EMIF_SDRAMTIM_V
        ;****************************************************************
      ||    mvkl  EMIF_SDRAMTIM,A4      
      ||    mvkl  EMIF_SDRAMTIM_V,B4    ;

            mvkh  EMIF_SDRAMTIM,A4
      ||    mvkh  EMIF_SDRAMTIM_V,B4

            stw   B4,*A4

        ;****************************************************************
        ; *EMIF_SDRAMEXT = EMIF_SDRAMEXT_V
        ;****************************************************************
      ||    mvkl  EMIF_SDRAMEXT,A4      
      ||    mvkl  EMIF_SDRAMEXT_V,B4    ;

            mvkh  EMIF_SDRAMEXT,A4
      ||    mvkh  EMIF_SDRAMEXT_V,B4

            stw   B4,*A4

;****************************************************************************
; copy sections
;****************************************************************************
    mvkl  FLASH_START,B4 ;flash start address ->B4
    mvkh  FLASH_START,B4   
      	
	mvkl  CODE_START,A4 ;apps code start address ->A4
	mvkh  CODE_START,A4
	zero  A1
	
_boot_loop1:
	ldb   *B4++,B5       ; flash read
	mvkl  CODE_SIZE-4,B6 ; B6 = BOOT_SIZE -1024
	
	add   1,A1,A1          ;A1+=1,inc outer counter
	||    mvkh  CODE_SIZE-4,B6
	
	cmplt  A1,B6,B0
	nop    
	stb   B5,*A4++
	[B0]  b     _boot_loop1
	nop   5
	
	mvkl .S2 _c_int00, B0
	mvkh .S2 _c_int00, B0
	B    .S2 B0
	nop   5