📄 2407.h
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/*************************************************************************
/* File name: 2407.h
/*
/* Description: 240x register definitions, Bit codes for BIT instruction
/*************************************************************************
/* 240x CPU core registers*/
#define IMR *(int *)0x0004 /* Interrupt Mask Register*/
#define IFR *(int *)0x0006 /* Interrupt Flag Register*/
/* System configuration and interrupt registers*/
#define SCSR1 *(int *)0x7018 /* System Control & Status register. 1 */
#define SCSR2 *(int *)0x7019 /* System Control & Status register. 2*/
#define DINR *(int *)0x701C /* Device Identification Number register. */
#define PIVR *(int *)0x701E /* Peripheral Interrupt Vector register. */
#define PIRQR0 *(int *)0x7010 /* Peripheral Interrupt Request register 0*/
#define PIRQR1 *(int *)0x7011 /* Peripheral Interrupt Request register 1*/
#define PIRQR2 *(int *)0x7012 /* Peripheral Interrupt Request register 2*/
#define PIACKR0 *(int *)0x7014 /* Peripheral Interrupt Acknowledge register 0 */
#define PIACKR1 *(int *)0x7015 /* Peripheral Interrupt Acknowledge register 1 */
#define PIACKR2 *(int *)0x7016 /* Peripheral Interrupt Acknowledge register 2*/
/* External interrupt configuration registers */
#define XINT1CR *(int *)0x7070 /* External interrupt 1 control register*/
#define XINT2CR *(int *)0x7071 /* External interrupt 2 control register*/
/* Digital I/O registers*/
#define MCRA *(int *)0x7090 /* I/O Mux Control Register A*/
#define MCRB *(int *)0x7092 /* I/O Mux Control Register B*/
#define MCRC *(int *)0x7094 /* I/O Mux Control Register C*/
#define PADATDIR *(int *)0x7098 /* I/O port A Data & Direction register*/
#define PBDATDIR *(int *)0x709A /* I/O port B Data & Direction register*/
#define PCDATDIR *(int *)0x709C /* I/O port C Data & Direction register*/
#define PDDATDIR *(int *)0x709E /* I/O port D Data & Direction register*/
#define PEDATDIR *(int *)0x7095 /* I/O port E Data & Direction register*/
#define PFDATDIR *(int *)0x7096 /* I/O port F Data & Direction register*/
/* Watchdog (WD) registers*/
#define WDCNTR *(int *)0x7023 /* WD Counter register */
#define WDKEY *(int *)0x7025 /* WD Key register*/
#define WDCR *(int *)0x7029 /* WD Control register*/
/* ADC registers*/
#define ADCTRL1 *(int *)0x70A0 /* ADC Control register 1*/
#define ADCTRL2 *(int *)0x70A1 /* ADC Control register 2*/
#define MAXCONV *(int *)0x70A2 /* Maximum conversion channels register*/
#define CHSELSEQ1 *(int *)0x70A3 /* Channel select Sequencing control register 1*/
#define CHSELSEQ2 *(int *)0x70A4 /* Channel select Sequencing control register 2*/
#define CHSELSEQ3 *(int *)0x70A5 /* Channel select Sequencing control register 3*/
#define CHSELSEQ4 *(int *)0x70A6 /* Channel select Sequencing control register 4*/
#define AUTO_SEQ_SR *(int *)0x70A7 /* Auto杝equence status register*/
#define RESULT0 *(int *)0x70A8 /* Conversion result buffer register 0*/
#define RESULT1 *(int *)0x70A9 /* Conversion result buffer register 1*/
#define RESULT2 *(int *)0x70Aa /* Conversion result buffer register 2*/
#define RESULT3 *(int *)0x70Ab /* Conversion result buffer register 3 */
#define RESULT4 *(int *)0x70Ac /* Conversion result buffer register 4*/
#define RESULT5 *(int *)0x70Ad /* Conversion result buffer register 5*/
#define RESULT6 *(int *)0x70Ae /* Conversion result buffer register 6*/
#define RESULT7 *(int *)0x70Af /* Conversion result buffer register 7*/
#define RESULT8 *(int *)0x70B0 /* Conversion result buffer register 8*/
#define RESULT9 *(int *)0x70B1 /* Conversion result buffer register 9 */
#define RESULT10 *(int *)0x70B2 /* Conversion result buffer register 10*/
#define RESULT11 *(int *)0x70B3 /* Conversion result buffer register 11*/
#define RESULT12 *(int *)0x70B4 /* Conversion result buffer register 12*/
#define RESULT13 *(int *)0x70B5 /* Conversion result buffer register 13*/
#define RESULT14 *(int *)0x70B6 /* Conversion result buffer register 14*/
#define RESULT15 *(int *)0x70B7 /* Conversion result buffer register 15*/
#define CALIBRATION *(int *)0x70B8 /* Calib result, used to correct*/
/* subsequent conversions*/
/* SPI registers*/
#define SPICCR *(int *)0x7040 /* SPI Config Control register*/
#define SPICTL *(int *)0x7041 /* SPI Operation Control register*/
#define SPISTS *(int *)0x7042 /* SPI Status register*/
#define SPIBRR *(int *)0x7044 /* SPI Baud rate control register*/
#define SPIRXEMU *(int *)0x7046 /* SPI Emulation buffer register*/
#define SPIRXBUF *(int *)0x7047 /* SPI Serial receive buffer register*/
#define SPITXBUF *(int *)0x7048 /* SPI Serial transmit buffer register*/
#define SPIDAT *(int *)0x7049 /* SPI Serial data register*/
#define SPIPRI *(int *)0x704F /* SPI Priority control register*/
/* SCI registers*/
#define SCICCR *(int *)0x7050 /* SCI Communication control register */
#define SCICTL1 *(int *)0x7051 /* SCI Control register 1*/
#define SCIHBAUD *(int *)0x7052 /* SCI Baud Rate MS byte register */
#define SCILBAUD *(int *)0x7053 /* SCI Baud Rate LS byte register*/
#define SCICTL2 *(int *)0x7054 /* SCI Control register 2*/
#define SCIRXST *(int *)0x7055 /* SCI Receiver Status register*/
#define SCIRXEMU *(int *)0x7056 /* SCI Emulation Data Buffer register */
#define SCIRXBUF *(int *)0x7057 /* SCI Receiver Data buffer register*/
#define SCITXBUF *(int *)0x7059 /* SCI Transmit Data buffer register*/
#define SCIPRI *(int *)0x705F /* SCI Priority control register*/
/* Event Manager A (EVA) registers*/
#define GPTCONA *(int *)0x7400 /* GP Timer control register A*/
#define T1CNT *(int *)0x7401 /* GP Timer 1 counter register*/
#define T1CMPR *(int *)0x7402 /* GP Timer 1 compare register*/
#define T1PR *(int *)0x7403 /* GP Timer 1 period register*/
#define T1CON *(int *)0x7404 /* GP Timer 1 control register*/
#define T2CNT *(int *)0x7405 /* GP Timer 2 counter register*/
#define T2CMPR *(int *)0x7406 /* GP Timer 2 compare register*/
#define T2PR *(int *)0x7407 /* GP Timer 2 period register*/
#define T2CON *(int *)0x7408 /* GP Timer 2 control register*/
#define COMCONA *(int *)0x7411 /* Compare control register A */
#define ACTRA *(int *)0x7413 /* Full compare Action control register A*/
#define DBTCONA *(int *)0x7415 /* Dead朾and timer control register A */
#define CMPR1 *(int *)0x7417 /* Full compare unit compare register1 */
#define CMPR2 *(int *)0x7418 /* Full compare unit compare register2 */
#define CMPR3 *(int *)0x7419 /* Full compare unit compare register3 */
#define CAPCONA *(int *)0x7420 /* Capture control register A*/
#define CAPFIFOA *(int *)0x7422 /* Capture FIFO status register A */
#define CAP1FIFO *(int *)0x7423 /* Capture Channel 1 FIFO Top*/
#define CAP2FIFO *(int *)0x7424 /* Capture Channel 2 FIFO Top*/
#define CAP3FIFO *(int *)0x7425 /* Capture Channel 3 FIFO Top*/
#define CAP1FBOT *(int *)0x7427 /* Bottom reg. of capture FIFO stack 1*/
#define CAP2FBOT *(int *)0x7428 /* Bottom reg. of capture FIFO stack 2*/
#define CAP3FBOT *(int *)0x7429 /* Bottom reg. of capture FIFO stack 3 */
#define EVAIMRA *(int *)0x742C /* Group A Interrupt Mask Register */
#define EVAIMRB *(int *)0x742D /* Group B Interrupt Mask Register */
#define EVAIMRC *(int *)0x742E /* Group C Interrupt Mask Register */
#define EVAIFRA *(int *)0x742F /* Group A Interrupt Flag Register*/
#define EVAIFRB *(int *)0x7430 /* Group B Interrupt Flag Register*/
#define EVAIFRC *(int *)0x7431 /* Group C Interrupt Flag Register*/
/* Event Manager B (EVB) registers*/
#define GPTCONB *(int *)0x7500 /* GP Timer control register B */
#define T3CNT *(int *)0x7501 /* GP Timer 3 counter register */
#define T3CMPR *(int *)0x7502 /* GP Timer 3 compare register */
#define T3PR *(int *)0x7503 /* GP Timer 3 period register */
#define T3CON *(int *)0x7504 /* GP Timer 3 control register*/
#define T4CNT *(int *)0x7505 /* GP Timer 4 counter register */
#define T4CMPR *(int *)0x7506 /* GP Timer 4 compare register*/
#define T4PR *(int *)0x7507 /* GP Timer 4 period register*/
#define T4CON *(int *)0x7508 /* GP Timer 4 control register*/
#define COMCONB *(int *)0x7511 /* Compare control register B */
#define ACTRB *(int *)0x7513 /* Full compare Action control register B*/
#define DBTCONB *(int *)0x7515 /* Dead朾and timer control register B*/
#define CMPR4 *(int *)0x7517 /* Full compare unit compare register4*/
#define CMPR5 *(int *)0x7518 /* Full compare unit compare register5*/
#define CMPR6 *(int *)0x7519 /* Full compare unit compare register6*/
#define CAPCONB *(int *)0x7520 /* Capture control register B*/
#define CAPFIFOB *(int *)0x7522 /* Capture FIFO status register B */
#define CAP4FIFO *(int *)0x7523 /* Capture Channel 4 FIFO Top*/
#define CAP5FIFO *(int *)0x7524 /* Capture Channel 5 FIFO Top*/
#define CAP6FIFO *(int *)0x7525 /* Capture Channel 6 FIFO Top */
#define CAP4FBOT *(int *)0x7527 /* Bottom reg. of capture FIFO stack 4 */
#define CAP5FBOT *(int *)0x7527 /* Bottom reg. of capture FIFO stack 5*/
#define CAP6FBOT *(int *)0x7527 /* Bottom reg. of capture FIFO stack 6*/
#define EVBIMRA *(int *)0x752C /* Group A Interrupt Mask Register */
#define EVBIMRB *(int *)0x752D /* Group B Interrupt Mask Register */
#define EVBIMRC *(int *)0x752E /* Group C Interrupt Mask Register */
#define EVBIFRA *(int *)0x752F /* Group A Interrupt Flag Register*/
#define EVBIFRB *(int *)0x7530 /* Group B Interrupt Flag Register*/
#define EVBIFRC *(int *)0x7531 /* Group C Interrupt Flag Register*/
/* CAN registers*/
#define CANMDER *(int *)0x7100 /* CAN Mailbox Direction/Enable register*/
#define CANTCR *(int *)0x7101 /* CAN Transmission Control register*/
#define CANRCR *(int *)0x7102 /* CAN Recieve Control register */
#define CANMCR *(int *)0x7103 /* CAN Master Control register */
#define CANBCR2 *(int *)0x7104 /* CAN Bit Config register 2 */
#define CANBCR1 *(int *)0x7105 /* CAN Bit Config register 1*/
#define CANESR *(int *)0x7106 /* CAN Error Status register*/
#define CANGSR *(int *)0x7107 /* CAN Global Status register*/
#define CANCEC *(int *)0x7108 /* CAN Trans and Rcv Err counters */
#define CANIFR *(int *)0x7109 /* CAN Interrupt Flag Register*/
#define CANIMR *(int *)0x710a /* CAN Interrupt Mask Register */
#define CANLAM0H *(int *)0x710b /* CAN Local Acceptance Mask MBX0/1 */
#define CANLAM0L *(int *)0x710c /* CAN Local Acceptance Mask MBX0/1*/
#define CANLAM1H *(int *)0x710d /* CAN Local Acceptance Mask MBX2/3 */
#define CANLAM1L *(int *)0x710e /* CAN Local Acceptance Mask MBX2/3*/
#define CANMSGID0L *(int *)0x7200 /* CAN Message ID for mailbox 0 (lower 16 bits)*/
#define CANMSGID0H *(int *)0x7201 /* CAN Message ID for mailbox 0 (upper 16 bits)*/
#define CANMSGCTRL0 *(int *)0x7202 /* CAN RTR and DLC*/
#define CANMBX0A *(int *)0x7204 /* CAN 2 of 8 bytes of Mailbox 0*/
#define CANMBX0B *(int *)0x7205 /* CAN 2 of 8 bytes of Mailbox 0*/
#define CANMBX0C *(int *)0x7206 /* CAN 2 of 8 bytes of Mailbox 0 */
#define CANMBX0D *(int *)0x7207 /* CAN 2 of 8 bytes of Mailbox 0 */
#define CANMSGID1L *(int *)0x7208 /* CAN Message ID for mailbox 1 (lower 16 bits)*/
#define CANMSGID1H *(int *)0x7209 /* CAN Message ID for mailbox 1 (upper 16 bits)*/
#define CANMSGCTRL1 *(int *)0x720A /* CAN RTR and DLC*/
#define CANMBX1A *(int *)0x720C /* CAN 2 of 8 bytes of Mailbox 1*/
#define CANMBX1B *(int *)0x720D /* CAN 2 of 8 bytes of Mailbox 1*/
#define CANMBX1C *(int *)0x720E /* CAN 2 of 8 bytes of Mailbox 1*/
#define CANMBX1D *(int *)0x720F /* CAN 2 of 8 bytes of Mailbox 1*/
#define CANMSGID2L *(int *)0x7210 /* CAN Message ID for mailbox 2 (lower 16 bits)*/
#define CANMSGID2H *(int *)0x7211 /* CAN Message ID for mailbox 2 (upper 16 bits)*/
#define CANMSGCTRL2 *(int *)0x7212 /* CAN RTR and DLC */
#define CANMBX2A *(int *)0x7214 /* CAN 2 of 8 bytes of Mailbox 2*/
#define CANMBX2B *(int *)0x7215 /* CAN 2 of 8 bytes of Mailbox 2*/
#define CANMBX2C *(int *)0x7216 /* CAN 2 of 8 bytes of Mailbox 2*/
#define CANMBX2D *(int *)0x7217 /* CAN 2 of 8 bytes of Mailbox 2*/
#define CANMSGID3L *(int *)0x7218 /* CAN Message ID for mailbox 3 (lower 16 bits)*/
#define CANMSGID3H *(int *)0x7219 /* CAN Message ID for mailbox 3 (upper 16 bits)*/
#define CANMSGCTRL3 *(int *)0x721A /* CAN RTR and DLC*/
#define CANMBX3A *(int *)0x721C /* CAN 2 of 8 bytes of Mailbox 3 */
#define CANMBX3B *(int *)0x721D /* CAN 2 of 8 bytes of Mailbox 3 */
#define CANMBX3C *(int *)0x721E /* CAN 2 of 8 bytes of Mailbox 3*/
#define CANMBX3D *(int *)0x721F /* CAN 2 of 8 bytes of Mailbox 3 */
#define CANMSGID4L *(int *)0x7220 /* CAN Message ID for mailbox 4 (lower 16 bits)*/
#define CANMSGID4H *(int *)0x7221 /* CAN Message ID for mailbox 4 (upper 16 bits)*/
#define CANMSGCTRL4 *(int *)0x7222 /* CAN RTR and DLC*/
#define CANMBX4A *(int *)0x7224 /* CAN 2 of 8 bytes of Mailbox 4*/
#define CANMBX4B *(int *)0x7225 /* CAN 2 of 8 bytes of Mailbox 4*/
#define CANMBX4C *(int *)0x7226 /* CAN 2 of 8 bytes of Mailbox 4*/
#define CANMBX4D *(int *)0x7227 /* CAN 2 of 8 bytes of Mailbox 4*/
#define CANMSGID5L *(int *)0x7228 /* CAN Message ID for mailbox 5 (lower 16 bits)*/
#define CANMSGID5H *(int *)0x7229 /* CAN Message ID for mailbox 5 (upper 16 bits)*/
#define CANMSGCTRL5 *(int *)0x722A /* CAN RTR and DLC*/
#define CANMBX5A *(int *)0x722C /* CAN 2 of 8 bytes of Mailbox 5 */
#define CANMBX5B *(int *)0x722D /* CAN 2 of 8 bytes of Mailbox 5 */
#define CANMBX5C *(int *)0x722E /* CAN 2 of 8 bytes of Mailbox 5 */
#define CANMBX5D *(int *)0x722F /* CAN 2 of 8 bytes of Mailbox 5 */
/*--------------------------------------------------- */
/*I/O space mapped registers */
/*--------------------------------------------------- */
#define WSGR *(int *)0x0FFFF /* Wait朣tate Generator Control register */
#define FCMR *(int *)0x0FF0F /* Flash control mode register */
/*--------------------------------------------------- */
/*Bit codes for Test bit instruction (BIT) (15 Loads bit 0 into TC)*/
/*---------------------------------------------------*/
#define BIT15 0x0000 /* Bit Code for 15*/
#define BIT14 0x0001 /* Bit Code for 14*/
#define BIT13 0x0002 /* Bit Code for 13*/
#define BIT12 0x0003 /* Bit Code for 12*/
#define BIT11 0x0004 /* Bit Code for 11*/
#define BIT10 0x0005 /* Bit Code for 10 */
#define BIT9 0x0006 /* Bit Code for 9 */
#define BIT8 0x0007 /* Bit Code for 8 */
#define BIT7 0x0008 /* Bit Code for 7 */
#define BIT6 0x0009 /* Bit Code for 6 */
#define BIT5 0x000A /* Bit Code for 5*/
#define BIT4 0x000B /* Bit Code for 4 */
#define BIT3 0x000C /* Bit Code for 3 */
#define BIT2 0x000D /* Bit Code for 2*/
#define BIT1 0x000E /* Bit Code for 1*/
#define BIT0 0x000F /* Bit Code for 0*/
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