afe.c

DSP 5409 plc应用程序,调试通过,是用在电力线通讯上的演示程序.

		MCBSP_SUBREG_WRITE(MCBSP_PORT2, SPCR1_SUBADDR, spcr1_ctrl);
		MCBSP_SUBREG_WRITE(MCBSP_PORT2, SPCR2_SUBADDR, spcr2_ctrl);
		break;
	}

	return;
}
#endif


#if COMPILE_MODE == DSP_COMPILE
//==========================================================================================
// Function:		ConfigureAFE()
//
// Description: 	This function configures the ADE1230 Analog Front-End  as well as the
//					 MCBSP ports and the DMA channels which talk to them.  
//					It should be called during board initialization.
//					The DMA channel gets configured to read the correct number of channels
//                  (QUAD_CHANNELS +LOCAL_CHANNELS) the correct number of times 
//					(OVERSAMPLE_RATE).
//
//	Assumptions:	* There are two ADC MCBSP busses: one for local sensors, one for remote.
//					* All the A/D converters on the local bus are the same model.
//					* All the A/D converters on the remote bus are the same model.
//					* The remote and local ADCs are similar enough that they can use the 
//					  same MCBSP settings but slightly different ADC settings.
// Revision History:
//==========================================================================================
u16	ConfigureAFE (void)
{
	// ACHTUNG!  Please don't move these #defines to a .h file.  I used them here instead
	// of 'const' statements because they save code space.
	// MCBSP = Multi-Channel Buffered Serial Port

#if (AFE_RX_FORMAT == 24)	// Receive two 24-bit words
	// MCBSP Serial Port Control Register 1
	// Enable receive port with standard settings except left-justified.
	#define SPCR1_CTRL	( (DLB_DISABLE<<DLB) | (RXJUST_LJZF<<RJUST) 					\
						| (CLK_STOP_DISABLED<<CLKSTP) | (DX_ENABLE_OFF<<DXENA)			\
						| (ABIS_DISABLE<<ABIS) | (INTM_RDY<<RINTM) | (RX_ENABLE<<RRST)	)
#else
	// MCBSP Serial Port Control Register 1
	// Enable receive port with standard settings.
	#define SPCR1_CTRL	( (DLB_DISABLE<<DLB) | (RXJUST_RJZF<<RJUST) 					\
						| (CLK_STOP_DISABLED<<CLKSTP) | (DX_ENABLE_OFF<<DXENA)			\
						| (ABIS_DISABLE<<ABIS) | (INTM_RDY<<RINTM) | (RX_ENABLE<<RRST)	)
#endif

	// MCBSP Serial Port Control Register 2
	// Enable transmit port with standard settings.
	#define	SPCR2_CTRL	( (SP_FREE_ON<<FREE) | (SOFT_DISABLE<<SOFT)						\
						| (FRAME_GEN_ENABLE<<FRST) | (SRG_ENABLE<<GRST) 				\
						| (INTM_RDY<<XINTM) | (RX_ENABLE<<XRST)							)

	// MCBSP Pin Control Register
	// Configure pins as serial ports instead of GPIOs, 
	// Generate transmit frame-sync on the XFS pin using internal sample rate generator.
	// Receive frame-sync is input from RFS pin (which is wired to XFS on board).
	#define	PCR_CTRL	( (IO_DISABLE<<13)     | (IO_DISABLE<<12) 						\
		  				| (FSYNC_MODE_INT<<11) | (FSYNC_MODE_EXT<<10)					\
		  			 	| (CLK_MODE_INT<<9)    | (CLK_MODE_EXT<<8) 						\
    	  			 	| (FSYNC_POL_HIGH<<3)  | (FSYNC_POL_HIGH<<2)					\
		  			 	| (CLKX_POL_FALLING<<1)| (CLKR_POL_FALLING<<0)					)


#if (AFE_RX_FORMAT == 24)	// Receive two 24-bit words
	// MCBSP Receive Control Register 1
	// 2 words/frame, 24-bit word	
	#define	RCR1_CTRL	((2-1)<<RFRLEN1 | (WORD_LENGTH_24<<RWDLEN1)		)
#else					// Receive three 16-bit words
	#if (SEND_TWICE == TRUE)
		// MCBSP Receive Control Register 1
		// 1 words/frame, 16-bit word
		#define	RCR1_CTRL	( (1-1)<<RFRLEN1 | (WORD_LENGTH_16<<RWDLEN1)	)
	#else
		// MCBSP Receive Control Register 1
		// 3 words/frame, 16-bit words
		#define	RCR1_CTRL	( (3-1)<<RFRLEN1 | (WORD_LENGTH_16<<RWDLEN1)	)
	#endif
#endif

	// MCBSP Receive Control Register 2
	// Standard
	#define	RCR2_CTRL	( (SINGLE_PHASE<<RPHASE) | (0<<RFRLEN2) | (0<<RWDLEN2) 			\
    					| (NO_COMPAND_MSB_1ST<<RCOMPAND) | (NO_FRAME_IGNORE<<RFIG) 		\
    					| (DATA_DELAY2<<RDATDLY)										)


#if (AFE_TX_FORMAT == 24)	// Send two 24-bit words
	// MCBSP Transmit Control Register 1
	// 2 words/frame, 24-bit word	
	#define	XCR1_CTRL	((2-1)<<XFRLEN1 | (WORD_LENGTH_24<<XWDLEN1)		)
#else					// Send three 16-bit words
	// MCBSP Transmit Control Register 1
	// 3 words/frame, 16-bit words
	#define	XCR1_CTRL	( (3-1)<<XFRLEN1 | (WORD_LENGTH_16<<XWDLEN1)	)
#endif

    // MCBSP Transmit Control Register 2
	// Standard
	#define	XCR2_CTRL	( (SINGLE_PHASE<<XPHASE) | (0<<XFRLEN1) | (0<<XWDLEN1) 			\
    					| (NO_COMPAND_MSB_1ST<<XCOMPAND) | (NO_FRAME_IGNORE<<XFIG) 		\
    					| (DATA_DELAY1<<XDATDLY)										)
 
	// MCBSP Sample Rate Generator Register 1
	// Frame-sync pulse 1 CLKG period wide, set Serial clock rate 
	#define	SRGR1_CTRL	((2-1)<<FWID) | ((SER_CLK_DIV-1)<<CLKGDV)				

     						
	//#define SRGR2_CTRL_NORM = defined in sensor.h
	//#define SRGR2_CTRL_DMA= defined in sensor.h	
				

	// This next group of registers are all set to zero because we are not using the 
	// Multi-Channel features of the MCBSP.  
	// We will instead use the DMA sequencer to scan through the ADC input channels.

	// MCBSP Multichannel Register 1
	#define	MCR1_CTRL	0
    			 
	// MCBSP Multichannel Register 2
	#define	MCR2_CTRL	0
    	
    // MCBSP Receive Channel Enable Register Part A			 
	#define	RCERA_CTRL	0
    
    // MCBSP Receive Channel Enable Register Part B				
	#define	RCERB_CTRL	0
    
    // MCBSP Transmit Channel Enable Register Part A			
	#define	XCERA_CTRL	0

    // MCBSP Transmit Channel Enable Register Part B				
	#define	XCERB_CTRL	0

	//--------------------------------------------------------------------------------------

	u16		uPortNum = AFE_MCBSP;		//
	u16		uStatus = SUCCESS;			// Return value.

 	#ifdef FLOW
		LOG_printf(&Trace, "Entered ConfigureAFE()");
	#endif


	// Initialize the MCBSP port which is connected to the AFE
	InitMCBSP(uPortNum,   SPCR1_CTRL,      SPCR2_CTRL,   PCR_CTRL,
			  RCR1_CTRL,  RCR2_CTRL,        XCR1_CTRL,  XCR2_CTRL,
			  SRGR1_CTRL, SRGR2_CTRL_NORM,  MCR1_CTRL,  MCR2_CTRL,
			  RCERA_CTRL, RCERB_CTRL,      XCERA_CTRL, XCERB_CTRL);


	// Shut off frame sync generation (FS)
	MCBSP_SUBREG_BITWRITE(uPortNum, SPCR2_SUBADDR, FRST, FRST_SZ, 0);



	// ---------- DMA Configuration ---------------
	SET_REG(DMPREC, 0);			//!!!TEMP Disable all DMA channels before configuring them
	DMA_reset();				// Reset all DMA registers.

//NORMAL 	// All channels are disabled for now.  DMA will keep running when emulator is paused.
//NORMAL 	// DMA Channels 4 and 2 have high priority.
//NORMAL 	// Interrupts will be directed to HWI_SINT 6 through 13.
//NORMAL 	#define DMPREC_INIT (	(RUN<<DMA_FREE) | (LO<<DPRC5) | (HI<<DPRC4) | (LO<<DPRC3) \
//NORMAL 						 					| (HI<<DPRC2) | (LO<<DPRC1) | (LO<<DPRC0) \
//NORMAL 					   | (INTOSEL2<<INTSEL) | (DIS<<DE5)  |  (DIS<<DE4) | (DIS<<DE3)  \
//NORMAL 											| (DIS<<DE2)  |  (DIS<<DE1) | (DIS<<DE0) )	  

	// All channels are disabled for now.  DMA will keep pause when emulator is paused. <<<!!!DEBUG
	// DMA Channels 4 and 2 have high priority.
	// Interrupts will be directed to HWI_SINT 6 through 13.
	#define DMPREC_INIT (	(STOP<<DMA_FREE) | (LO<<DPRC5) | (HI<<DPRC4) | (LO<<DPRC3) \
						 					| (HI<<DPRC2) | (LO<<DPRC1) | (LO<<DPRC0) \
					   | (INTOSEL2<<INTSEL) | (DIS<<DE5)  |  (DIS<<DE4) | (DIS<<DE3)  \
											| (DIS<<DE2)  |  (DIS<<DE1) | (DIS<<DE0) )	  

	SET_REG(DMPREC, DMPREC_INIT);

	return(uStatus);
}
#endif



#if COMPILE_MODE == DSP_COMPILE
//==========================================================================================
// Function:		ConfigureMCBSPDMA()
//
// Description: 	Configure the Multi-Channel Buffered Serial Port for DMA operations.
//					Generates a single frame-sync pulse per transmitted word.
//
// Revision History:
//==========================================================================================
void ConfigureMCBSPDMA(u16 uPortNum)
{
	RPTNOP(24*SER_CLK_DIV_SLOW);	// Wait 24 cycles of slow serial clock to ensure all 
									// previous transmissions are complete.  

	//-------------------------------------------------------------------------------------
	// Configure the MCBSP clocks and frame generators for DMA transmission mode.
	//-------------------------------------------------------------------------------------

	//Place transmit port in reset and turn off clock generator and frame sync generator.
	MCBSP_SUBREG_WRITE(uPortNum, SPCR2_SUBADDR, 0x0000);

	// Use the fast serial clock for these transfers
	MCBSP_SUBREG_WRITE(uPortNum, SRGR1_SUBADDR, SRGR1_CTRL_FAST);

	// Configure the MCBSP to transmit frame syncs due to DXR load
	MCBSP_SUBREG_WRITE(uPortNum, SRGR2_SUBADDR, SRGR2_CTRL_DMA);

	// Release clock generator from reset and wait 2 clock cycles -----
	MCBSP_SUBREG_BITWRITE(uPortNum, SPCR2_SUBADDR, GRST, GRST_SZ, 1);  //!!!TEMP!!!
	RPTNOP(2*SER_CLK_DIV);	// Wait 2 cycles of fast serial clock

	// Release transmitter from reset, enable frame sync.                 
	MCBSP_SUBREG_WRITE(uPortNum, SPCR2_SUBADDR, SPCR2_CTRL); 
	RPTNOP(2*SER_CLK_DIV);	// Wait 2 cycles of fast serial clock ??Is this Needed??

	return;
}
#endif  
  	     
  
#if COMPILE_MODE == DSP_COMPILE
//==========================================================================================
// Function:		DMAWriteAFE()
//
// Description: 	Use the DMA engine and MCBSP to transmit a block of Tx data to the AFE.
//
// Revision History:
//==========================================================================================
#if (AFE_TX_FORMAT == 24)	// Send two 24-bit words
void DMAWriteAFE(u32 *upADCCmdListAddr, u16 uArraySize)
#else					// Send three 16-bit words
void DMAWriteAFE(u16 *upADCCmdListAddr, u16 uArraySize)
#endif
{
//!!! Move to Regs54xx.h or DMA.h
#define DBLW_SNGL	0
#define DBLW_DBL	1


#define	AFE_DMA_MASK 	(EN<<DE5)	// Enable DMA channel 5


	//----- Disable the DMA Engine while we configure it -----
	DMPREC &= ~(AFE_DMA_MASK); 

	// Configure MCBSP for automatic periodic Frame Sync generation

	/****************************************************************/
	/* Place ports in reset - setting XRST & RRST to 0              */
	/*  and turning off clock generator and frame sync generator    */
	/****************************************************************/

	MCBSP_SUBREG_WRITE(AFE_MCBSP, SPCR1_SUBADDR, 0x0000);
	MCBSP_SUBREG_WRITE(AFE_MCBSP, SPCR2_SUBADDR, 0x0000);

 	// ----- Set the serial clock speed for these transfers -----
 	MCBSP_SUBREG_WRITE(AFE_MCBSP, SRGR1_SUBADDR, SRGR1_CTRL_FAST);

	// ----- Configure the MCBSP to transmit periodic frame syncs automatically
	MCBSP_SUBREG_WRITE(AFE_MCBSP, SRGR2_SUBADDR, SRGR2_CTRL_DMA);

	// ----- Configure the DMA channel which sends commands to the ADC. -----
//	// Generate an interrupt to the DSP at the end of the block transfer.
//	// Post-increment source from data space, leave data space destination unmodified.
//	// Generate an interrupt to the DSP at the end of the block transfer.
//	#define DMA_CONTROL_WRITE_ADC2	( (0<<AUTOINIT) | (1<<DINM) | (0<<IMOD) | (0<<CTMOD) \
//									| (1<<SIND)  	| (1<<DMS)  | (0<<DIND) | (1<<DMD) )


	// Post-increment source from data space, leave data space destination unmodified.
	// Auto-reload at end of block.  Generate interrupts at end of frame and end of block.
	#define DMA_CONTROL_WRITE_ADC2	( (1<<AUTOINIT) | (1<<DINM) | (1<<IMOD) | (0<<CTMOD) \
									| (1<<SIND)  	| (1<<DMS)  | (0<<DIND) | (1<<DMD) )
									
	DMA_SUBREG_WRITE(DMA_CHANNEL5, DMGSA_SUBADDR, (u32)(upADCCmdListAddr));//  DMA Global Source Address
	DMA_SUBREG_WRITE(DMA_CHANNEL5, DMGCR_SUBADDR, uArraySize-1);			//  DMA Global Element Count
	DMA_SUBREG_WRITE(DMA_CHANNEL5, DMGFR_SUBADDR, (1-1));					//  DMA Global Frame Count	


#if AFE_MCBSP == 0
	#define DMASYNC_XEVT	DMASYNC_XEVT0