📄 afe.c
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//==========================================================================================
// Filename: AFE.c
//
// Description: Functions related to the AFE-1230 Analog Front-End interface.
//
// Copyright (C) 2001 - 2003 Texas Instruments Incorporated
// Texas Instruments Proprietary Information
// Use subject to terms and conditions of TI Software License Agreement
//
// Revision History:
//==========================================================================================
// TI specific defines
#include "ofdm_modem.h"
#include "ofdm_datatypes.h"
#include "dma.h"
#include "mcbsp54.h"
#define INTERPOLATE TRUE // Interpolate halfway between values when transmitting in SEND_TWICE mode.
#if (INTERPOLATE == TRUE) // Make this semi-global, for use by FillAFETxBuff... functions.
i16 prevTemp = 0x8000;
#endif
#define CONTENTS_OF32(addr) \
(*((volatile unsigned long*)(addr)))
#define REG_READ32(addr) \
(CONTENTS_OF32(addr))
#define REG_WRITE32(addr,val) \
(CONTENTS_OF32(addr) = (val))
//------------------------------------------------------------------------------------------
// MCBSP Serial Clock Setup
//------------------------------------------------------------------------------------------
// MCBSP clock rate: MCLK = MIPS / SER_CLK_DIV
// AFE Sample Rate: Fs = MCLK / 24
// MCBSP Frame Sync Rate: FSR = MCLK/48
// For MIPS=150 and SER_CLK_DIV=20 ==> MCLK = 7.5 MHz, Fs = 312.5 kHz, FSR = 156.25 kHz
// 0dB -.2dB -3dB
// SER_CLK_DIV MCLK(MHz) Fs(kHz) FSR .25*Fs .28*Fs .31*Fs .38*Fs .5*Fs
// 1 150.00 6250.0 3125.0 1562.5 1750.0 1937.5 2375.0 3125.0
// 2 75.00 3125.0 1562.5 781.3 875.0 968.8 1187.5 1562.5
// 3 50.00 2083.3 1041.7 520.8 583.3 645.8 791.7 1041.7
// 4 37.50 1562.5 781.3 390.6 437.5 484.4 593.8 781.3
// 5 30.00 1250.0 625.0 312.5 350.0 387.5 475.0 625.0
// 6 25.00 1041.7 520.8 260.4 291.7 322.9 395.8 520.8
// 7 21.43 892.9 446.4 223.2 250.0 276.8 339.3 446.4
// 8 18.75 781.3 390.6 195.3 218.8 242.2 296.9 390.6
// 9 16.67 694.4 347.2 173.6 194.4 215.3 263.9 347.2
// 10 15.00 625.0 312.5 156.3 175.0 193.8 237.5 312.5
// 11 13.64 568.2 284.1 142.0 159.1 176.1 215.9 284.1
// 12 12.50 520.8 260.4 130.2 145.8 161.5 197.9 260.4
// 13 11.54 480.8 240.4 120.2 134.6 149.0 182.7 240.4
// 14 10.71 446.4 223.2 111.6 125.0 138.4 169.6 223.2
// 15 10.00 416.7 208.3 104.2 116.7 129.2 158.3 208.3
// 16 9.38 390.6 195.3 97.7<<< 109.4 121.1 148.4 195.3
// 17 8.82 367.6 183.8 91.9 102.9 114.0 139.7 183.8
// 18 8.33 347.2 173.6 86.8 97.2<<< 107.6 131.9 173.6
// 19 7.89 328.9 164.5 82.2 92.1 102.0 125.0 164.5
// 20 7.50 312.5 156.3 78.1 87.5 96.9<<< 118.8 156.3
// 21 7.14 297.6 148.8 74.4 83.3 92.3 113.1 148.8
// 22 6.82 284.1 142.0 71.0 79.5 88.1 108.0 142.0
// 23 6.52 271.7 135.9 67.9 76.1 84.2 103.3 135.9
// 24 6.25 260.4 130.2 65.1 72.9 80.7 99.0 130.2
// 25 6.00 250.0 125.0 62.5 70.0 77.5 95.0<<< 125.0
// 26 5.77 240.4 120.2 60.1 67.3 74.5 91.3 120.2
// 27 5.56 231.5 115.7 57.9 64.8 71.8 88.0 115.7
// 28 5.36 223.2 111.6 55.8 62.5 69.2 84.8 111.6
// 29 5.17 215.5 107.8 53.9 60.3 66.8 81.9 107.8
// 30 5.00 208.3 104.2 52.1 58.3 64.6 79.2 104.2
// 31 4.84 201.6 100.8 50.4 56.5 62.5 76.6 100.8
// 32 4.69 195.3 97.7 48.8 54.7 60.5 74.2 97.7
// 33 4.55 189.4 94.7 47.3 53.0 58.7 72.0 94.7<<<
// 34 4.41 183.8 91.9 46.0 51.5 57.0 69.9 91.9
// 35 4.29 178.6 89.3 44.6 50.0 55.4 67.9 89.3
// 36 4.17 173.6 86.8 43.4 48.6 53.8 66.0 86.8
// 37 4.05 168.9 84.5 42.2 47.3 52.4 64.2 84.5
// 38 3.95 164.5 82.2 41.1 46.1 51.0 62.5 82.2
// 39 3.85 160.3 80.1 40.1 44.9 49.7 60.9 80.1
// 40 3.75 156.3 78.1 39.1 43.8 48.4 59.4 78.1
#define SER_CLK_DIV 25 // 25 = 125 kHz
#if COMPILE_MODE == DSP_COMPILE
asm("SER_CLK_DIV .set 25");
#endif
#define SER_CLK_DIV_SLOW 25
#if COMPILE_MODE == DSP_COMPILE
asm("SER_CLK_DIV_SLOW .set 25");
#endif
// Serial clock sample rate generator setup.
#define SRGR1_CTRL_SLOW ((1-1)<<FWID) | ((SER_CLK_DIV_SLOW-1)<<CLKGDV)
#define SRGR1_CTRL_FAST ((1-1)<<FWID) | ((SER_CLK_DIV-1)<<CLKGDV)
//-------------------------------------------------------------------------------------
// Generate periodic Frame-Sync pulses 48 CLKG periods apart
// MCBSP Sample Rate Generator Register 2
// Serial clock free-running, derived from CPU clock
//-------------------------------------------------------------------------------------
#define SRGR2_CTRL_DMA ((GSYNC_OFF<<GSYNC) | (CLKS_POL_FALLING<<CLKSP) \
| (CLKSM_CPU<<CLKSM) |(FSX_FSG<<FSGM) | ((48-1)<<FPER))
// MCBSP Sample Rate Generator Register 2
// Serial clock free-running, derived from CPU clock,
// Frame-sync pulse sent due to DXR->XSR copy, with a width of 1 CLKG period
#define SRGR2_CTRL_NORM ((GSYNC_OFF<<GSYNC) | (CLKS_POL_FALLING<<CLKSP) \
| (CLKSM_CPU<<CLKSM) |(FSX_DXR_TO_XSR<<FSGM) | ((1-1)<<FPER))
#define MAX_MCBSP_WAIT (18*SER_CLK_DIV) // Max wait = 18 serial clock ticks
//==========================================================================================
// Function: DelayNus(N)
//
// Description: This function delays N microseconds. It locks out interrupts for 1 us
// at a time, so use cautiously in time-critical routines.
//
// Revision History:
//==========================================================================================
void DelayNus(u16 uN)
{
u16 i; // loop counter
for (i=0; i<uN; i++)
{
RPTNOP(MIPS-10); // Delay 1 us per loop (locks out interrupts)
}
}
//==========================================================================================
// Function: DelayNms(N)
//
// Description: This function delays N milliseconds. It locks out interrupts for 1 us
// at a time, so use cautiously in time-critical routines.
//
// Revision History:
//==========================================================================================
void DelayNms(u16 uN)
{
u16 i; // loop counter
for (i=0; i<uN; i++)
{
DelayNus(1000); // Delay 1 ms per loop
}
}
#if COMPILE_MODE == DSP_COMPILE
//==========================================================================================
// Function: InitMCBSP()
//
// Description: This function initializes a Multi-Channel Buffered Serial Port (MCBSP).
// It replaces the mcbsp_init function included in mcbsp54.h which did not
// properly initialize the SPCR1 and SPCR2 registers.
//
// Revision History:
//==========================================================================================
void InitMCBSP(u16 port_no, u16 spcr1_ctrl, u16 spcr2_ctrl, u16 pcr_ctrl,
u16 rcr1_ctrl, u16 rcr2_ctrl, u16 xcr1_ctrl, u16 xcr2_ctrl,
u16 srgr1_ctrl, u16 srgr2_ctrl, u16 mcr1_ctrl, u16 mcr2_ctrl,
u16 rcera_ctrl, u16 rcerb_ctrl, u16 xcera_ctrl, u16 xcerb_ctrl)
{
#define MCBSP_PORT0 0
#define MCBSP_PORT1 1
#define MCBSP_PORT2 2
switch (port_no)
{
case MCBSP_PORT0:
/****************************************************************/
/* Place port in reset - setting XRST & RRST to 0 */
/****************************************************************/
MCBSP_SUBREG_WRITE(MCBSP_PORT0, SPCR1_SUBADDR, 0x0000);
MCBSP_SUBREG_WRITE(MCBSP_PORT0, SPCR2_SUBADDR, 0x0000);
/****************************************************************/
/* Set values of all control registers */
/****************************************************************/
MCBSP_SUBREG_WRITE(MCBSP_PORT0, SPCR1_SUBADDR, (spcr1_ctrl & 0xFFFE));
MCBSP_SUBREG_WRITE(MCBSP_PORT0, SPCR2_SUBADDR, (spcr2_ctrl & 0xFFFE));
MCBSP_SUBREG_WRITE(MCBSP_PORT0, PCR_SUBADDR, pcr_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT0, RCR1_SUBADDR, rcr1_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT0, RCR2_SUBADDR, rcr2_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT0, XCR1_SUBADDR, xcr1_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT0, XCR2_SUBADDR, xcr2_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT0, SRGR1_SUBADDR, srgr1_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT0, SRGR2_SUBADDR, srgr2_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT0, MCR1_SUBADDR, mcr1_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT0, MCR2_SUBADDR, mcr2_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT0, RCERA_SUBADDR, rcera_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT0, RCERB_SUBADDR, rcerb_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT0, XCERA_SUBADDR, xcera_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT0, XCERB_SUBADDR, xcerb_ctrl);
/****************************************************************/
/* Release clock generator from reset and wait 2 clock cycles */
/****************************************************************/
MCBSP_SUBREG_BITWRITE(MCBSP_PORT0, SPCR2_SUBADDR, GRST, GRST_SZ, 1);
RPTNOP(2*100/20); // Wait 2 cycles on 100 MIPS DSP & 20 MHz serial clock
/****************************************************************/
/* Release receiver and transmitter from reset */
/****************************************************************/
MCBSP_SUBREG_WRITE(MCBSP_PORT0, SPCR1_SUBADDR, spcr1_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT0, SPCR2_SUBADDR, spcr2_ctrl);
break;
case MCBSP_PORT1:
/****************************************************************/
/* Place port in reset - setting XRST & RRST to 0 */
/****************************************************************/
MCBSP_SUBREG_WRITE(MCBSP_PORT1, SPCR1_SUBADDR, 0x0000);
MCBSP_SUBREG_WRITE(MCBSP_PORT1, SPCR2_SUBADDR, 0x0000);
/****************************************************************/
/* Set values of all control registers */
/****************************************************************/
MCBSP_SUBREG_WRITE(MCBSP_PORT1, SPCR1_SUBADDR, (spcr1_ctrl & 0xFFFE));
MCBSP_SUBREG_WRITE(MCBSP_PORT1, SPCR2_SUBADDR, (spcr2_ctrl & 0xFFFE));
MCBSP_SUBREG_WRITE(MCBSP_PORT1, PCR_SUBADDR, pcr_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT1, RCR1_SUBADDR, rcr1_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT1, RCR2_SUBADDR, rcr2_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT1, XCR1_SUBADDR, xcr1_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT1, XCR2_SUBADDR, xcr2_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT1, SRGR1_SUBADDR, srgr1_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT1, SRGR2_SUBADDR, srgr2_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT1, MCR1_SUBADDR, mcr1_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT1, MCR2_SUBADDR, mcr2_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT1, RCERA_SUBADDR, rcera_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT1, RCERB_SUBADDR, rcerb_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT1, XCERA_SUBADDR, xcera_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT1, XCERB_SUBADDR, xcerb_ctrl);
/****************************************************************/
/* Release clock generator from reset and wait 2 clock cycles */
/****************************************************************/
MCBSP_SUBREG_BITWRITE(MCBSP_PORT1, SPCR2_SUBADDR, GRST, GRST_SZ, 1);
RPTNOP(2*100/20); // Wait 2 cycles on 100 MIPS DSP & 20 MHz serial clock
/****************************************************************/
/* Release receiver and transmitter from reset */
/****************************************************************/
MCBSP_SUBREG_WRITE(MCBSP_PORT1, SPCR1_SUBADDR, spcr1_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT1, SPCR2_SUBADDR, spcr2_ctrl);
break;
case MCBSP_PORT2:
/****************************************************************/
/* Place port in reset - setting XRST & RRST to 0 */
/****************************************************************/
MCBSP_SUBREG_WRITE(MCBSP_PORT2, SPCR1_SUBADDR, 0x0000);
MCBSP_SUBREG_WRITE(MCBSP_PORT2, SPCR2_SUBADDR, 0x0000);
/****************************************************************/
/* Set values of all control registers */
/****************************************************************/
MCBSP_SUBREG_WRITE(MCBSP_PORT2, SPCR1_SUBADDR, (spcr1_ctrl & 0xFFFE));
MCBSP_SUBREG_WRITE(MCBSP_PORT2, SPCR2_SUBADDR, (spcr2_ctrl & 0xFFFE));
MCBSP_SUBREG_WRITE(MCBSP_PORT2, PCR_SUBADDR, pcr_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT2, RCR1_SUBADDR, rcr1_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT2, RCR2_SUBADDR, rcr2_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT2, XCR1_SUBADDR, xcr1_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT2, XCR2_SUBADDR, xcr2_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT2, SRGR1_SUBADDR, srgr1_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT2, SRGR2_SUBADDR, srgr2_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT2, MCR1_SUBADDR, mcr1_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT2, MCR2_SUBADDR, mcr2_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT2, RCERA_SUBADDR, rcera_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT2, RCERB_SUBADDR, rcerb_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT2, XCERA_SUBADDR, xcera_ctrl);
MCBSP_SUBREG_WRITE(MCBSP_PORT2, XCERB_SUBADDR, xcerb_ctrl);
/****************************************************************/
/* Release clock generator from reset and wait 2 clock cycles */
/****************************************************************/
MCBSP_SUBREG_BITWRITE(MCBSP_PORT2, SPCR2_SUBADDR, GRST, GRST_SZ, 1);
RPTNOP(2*100/20); // Wait 2 cycles on 100 MIPS DSP & 20 MHz serial clock
/****************************************************************/
/* Release receiver and transmitter from reset */
/****************************************************************/
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