📄 regs54xx.h
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#define BNKCMP_SZ 4
#define PS_DS 11
#define PS_DS_SZ 1
#define HBH 2
#define HBH_SZ 1
#define BH 1
#define BH_SZ 1
#define EXIO 0
#define EXIO_SZ 1
/*-------------------------------------------------------------------*/
/* Define bitfields for Interruput Mask Register */
/*-------------------------------------------------------------------*/
#define INT0 0
#define INT1 1
#define INT2 2
#define TINT0 3
#define RINT0 4
#define XINT0 5
#define TINT1 7
#define INT3 8
#define HPI 9
#define RINT1 10
#define XINT1 11
#define DMAC0 6
#define DMAC1 7
#define DMAC2 10
#define DMAC3 11
#define DMAC4 12
#define DMAC5 13
/*-------------------------------------------------------------*/
/* DEFINE DATA STRUCTURE FOR HOST PORT INTERFACE CONTROL REG */
/*-------------------------------------------------------------*/
#define BOB 0
#define SMOD 1
#define DSPINT 2
#define HINT 3
#define XHPIA 4
/******************************************************************/
/* Define Interrupt Flag and Interrupt Mask Registers */
/******************************************************************/
#define IMR *(volatile unsigned int*)0x00
#define IMR_ADDR 0x0
#define IFR *(volatile unsigned int*)0x01
#define IFR_ADDR 0x1
/******************************************************************/
/* NOTE: YOU CAN ACCESS THESE REGISTERS IN THIS MANNER ONLY */
/* IF THE SUBADDRESS REGISTER HAS BEEN DEFINED ALREADY */
/******************************************************************/
/******************************************************************/
/* MultiChannel Buffer Serial 0 defined for 54XX */
/******************************************************************/
#define SPCR10 *(volatile unsigned int*)0x39
#define SPCR10_ADDR 0x39
#define SPCR20 *(volatile unsigned int*)0x39
#define SPCR20_ADDR 0x39
#define DRR20 *(volatile unsigned int*)0x20
#define DRR20_ADDR 0x20
#define DRR10 *(volatile unsigned int*)0x21
#define DRR10_ADDR 0x21
#define DXR20 *(volatile unsigned int*)0x22
#define DXR20_ADDR 0x22
#define DXR10 *(volatile unsigned int*)0x23
#define DXR10_ADDR 0x23
#define SPSA0_ADDR 0x38
#define SPSD0_ADDR 0x39
#define MCBSP_ACCSUB0_ADDR 0x39
/******************************************************************/
/* MultiChannel Buffer Serial 1 defined for 54XX */
/******************************************************************/
#define SPCR11 *(volatile unsigned int*)0x49
#define SPCR11_ADDR 0x49
#define SPCR21 *(volatile unsigned int*)0x49
#define SPCR21_ADDR 0x49
#define DRR21 *(volatile unsigned int*)0x40
#define DRR21_ADDR 0x40
#define DRR11 *(volatile unsigned int*)0x41
#define DRR11_ADDR 0x41
#define DXR21 *(volatile unsigned int*)0x42
#define DXR21_ADDR 0x42
#define DXR11 *(volatile unsigned int*)0x43
#define DXR11_ADDR 0x43
#define SPSA1_ADDR 0x48
#define SPSD1_ADDR 0x49
#define MCBSP_ACCSUB1_ADDR 0x49
/******************************************************************/
/* MultiChannel Buffer Serial 2 defined for 54XX */
/******************************************************************/
#define SPCR12 *(volatile unsigned int*)0x35
#define SPCR12_ADDR 0x35
#define SPCR22 *(volatile unsigned int*)0x35
#define SPCR22_ADDR 0x35
#define DRR22 *(volatile unsigned int*)0x30
#define DRR22_ADDR 0x30
#define DRR12 *(volatile unsigned int*)0x31
#define DRR12_ADDR 0x31
#define DXR22 *(volatile unsigned int*)0x32
#define DXR22_ADDR 0x32
#define DXR12 *(volatile unsigned int*)0x33
#define DXR12_ADDR 0x33
#define SPSA2_ADDR 0x34
#define SPSD2_ADDR 0x35
#define MCBSP_ACCSUB2_ADDR 0x35
/*******************************/
/* Register Definition MCBSP */
/*******************************/
/*-----------------PORT----------------|------2--------------|-----1------|------0------|*/
//Added by T. kyiamah
#define SPCR1_ADDR(port) ((port==2) ? SPCR12_ADDR: (port ? SPCR11_ADDR : SPCR10_ADDR))
#define SPCR2_ADDR(port) ((port==2) ? SPCR22_ADDR: (port ? SPCR21_ADDR : SPCR20_ADDR))
#define SPSA_ADDR(port) ((port==2) ? SPSA2_ADDR: (port ? SPSA1_ADDR : SPSA0_ADDR))
#define SPSD_ADDR(port) ((port==2) ? SPSD2_ADDR: (port ? SPSD1_ADDR : SPSD0_ADDR))
#define DRR2_ADDR(port) ((port==2) ? DRR22_ADDR: (port ? DRR21_ADDR : DRR20_ADDR))
#define DRR1_ADDR(port) ((port==2) ? DRR12_ADDR: (port ? DRR11_ADDR : DRR10_ADDR))
#define DXR2_ADDR(port) ((port==2) ? DXR22_ADDR: (port ? DXR21_ADDR : DXR20_ADDR))
#define DXR1_ADDR(port) ((port==2) ? DXR12_ADDR: (port ? DXR11_ADDR : DXR10_ADDR))
#define MCBSP_ACCSUB_ADDR(port) ((port==2) ? MCBSP_ACCSUB2_ADDR: (port ? MCBSP_ACCSUB1_ADDR : MCBSP_ACCSUB0_ADDR))
#define MCBSP0_SUBREG_WRITE(subaddr, value) \
((REG_WRITE(SPSA0_ADDR, subaddr)), (REG_WRITE(SPSD0_ADDR, value)))
#define MCBSP0_SUBREG_READ(subaddr) \
((REG_WRITE(SPSA0_ADDR, subaddr)), (REG_READ(SPSD0_ADDR)))
#define MCBSP0_SUBREG_BITWRITE(subaddr, bit, size, value) \
REG_WRITE(SPSD0_ADDR, (((REG_WRITE(SPSA0_ADDR, subaddr), REG_READ(SPSD0_ADDR)) & ~CREATE_FIELD(bit, size)) | ((value) << (bit)) ) )
#define MCBSP0_SUBREG_BITREAD(subaddr, bit, size) \
(unsigned int) (REG_WRITE(SPSA0_ADDR, subaddr), (REG_READ(SPSD0_ADDR) & CREATE_FIELD(bit, size)) >>(bit) )
#define MCBSP1_SUBREG_WRITE(subaddr, value) \
((REG_WRITE(SPSA1_ADDR, subaddr)), (REG_WRITE(SPSD1_ADDR, value)))
#define MCBSP1_SUBREG_READ(subaddr) \
((REG_WRITE(SPSA1_ADDR, subaddr)), (REG_READ(SPSD1_ADDR)))
#define MCBSP1_SUBREG_BITWRITE(subaddr, bit, size, value) \
REG_WRITE(SPSD1_ADDR, (((REG_WRITE(SPSA1_ADDR, subaddr), REG_READ(SPSD1_ADDR)) & ~CREATE_FIELD(bit, size)) | ((value) << (bit)) ) )
#define MCBSP1_SUBREG_BITREAD(subaddr, bit, size) \
(unsigned int) (REG_WRITE(SPSA1_ADDR, subaddr), (REG_READ(SPSD1_ADDR) & CREATE_FIELD(bit, size)) >>(bit) )
#define MCBSP2_SUBREG_WRITE(subaddr, value) \
((REG_WRITE(SPSA2_ADDR, subaddr)), (REG_WRITE(SPSD2_ADDR, value)))
#define MCBSP2_SUBREG_READ(subaddr) \
((REG_WRITE(SPSA2_ADDR, subaddr)), (REG_READ(SPSD2_ADDR)))
#define MCBSP2_SUBREG_BITWRITE(subaddr, bit, size, value) \
REG_WRITE(SPSD2_ADDR, (((REG_WRITE(SPSA2_ADDR, subaddr), REG_READ(SPSD2_ADDR)) & ~CREATE_FIELD(bit, size)) | ((value) << (bit)) ) )
#define MCBSP2_SUBREG_BITREAD(subaddr, bit, size) \
(unsigned int) (REG_WRITE(SPSA2_ADDR, subaddr), (REG_READ(SPSD2_ADDR) & CREATE_FIELD(bit, size)) >>(bit) )
#define SPCR1_SUBADDR 0x00
#define SPCR2_SUBADDR 0x01
#define RCR1_SUBADDR 0x02
#define RCR2_SUBADDR 0x03
#define XCR1_SUBADDR 0x04
#define XCR2_SUBADDR 0x05
#define SRGR1_SUBADDR 0x06
#define SRGR2_SUBADDR 0x07
#define MCR1_SUBADDR 0x08
#define MCR2_SUBADDR 0x09
#define RCERA_SUBADDR 0x0A
#define RCERB_SUBADDR 0x0B
#define XCERA_SUBADDR 0x0C
#define XCERB_SUBADDR 0x0D
#define PCR_SUBADDR 0x0E
/******************************************************************/
/* Direct Memory Access defined for 54XX */
/******************************************************************/
#define DMPRE (0x54)
#define DMSBA (0x55)
#define DMSAI (0x56)
#define DMSRCP (0x57)
#define DMDSTP (0x57)
#define DMGSA (0x57)
#define DMGDA (0x57)
#define DMGCR (0x57)
#define DMGFR (0x57)
#define DMFRI(reg) ((reg) ? 0x57:0x57)
#define DMIDX(reg) ((reg) ? 0x57:0x57)
#define DMSRC(channel) ((channel) ? 0x57:0x57)
#define DMDST(channel) ((channel) ? 0x57:0x57)
#define DMCTR(channel) ((channel) ? 0x57:0x57)
#define DMSEFC(channel) ((channel) ? 0x57:0x57)
#define DMMCR(channel) ((channel) ? 0x57:0x57
#define DMA_REG_READ(dma_subaddress, channel) (DMSAI(channel)=dma_subaddress), *(volatile unsigned int*) DMFRI(channel))
/*----------------------------------------------------------------*/
/* Data bitfields Period for DMPRE */
/*----------------------------------------------------------------*/
#define DPRC5 13
#define DPRC5_SZ 1
#define DPRC4 12
#define DPRC4_SZ 1
#define DPRC3 11
#define DPRC3_SZ 1
#define DPRC2 10
#define DPRC2_SZ 1
#define DPRC1 9
#define DPRC1_SZ 1
#define DPRC0 8
#define DPRC0_SZ 1
#define INTSEL 6
#define INTSEL_SZ 2
#define DE5 5
#define DE5_SZ 1
#define DE4 4
#define DE4_SZ 1
#define DE3 3
#define DE3_SZ 1
#define DE2 2
#define DE2_SZ 1
#define DE1 1
#define DE1_SZ 1
#define DE0 0
#define DE0_SZ 1
/*----------------------------------------------------------------*/
/* Data bitfields Period for DMSEFCn */
/*----------------------------------------------------------------*/
#define DSYN 12
#define DSYN_SZ 4
#define FRAME_CNT 0
#define FRAME_CNT_SZ 8
/*----------------------------------------------------------------*/
/* Data bitfields Period for Mode Control Register */
/*----------------------------------------------------------------*/
#define AUTOINIT 15
#define AUTOINIT_SZ 1
#define DINM 14
#define DINM_SZ 1
#define IMOD 13
#define IMOD_SZ 1
#define CTMOD 12
#define CTMOD_SZ 1
#define SIND 8
#define SIND_SZ 3
#define DMS 6
#define DMS_SZ 2
#define DIND 2
#define DIND_SZ 3
#define DMD 0
#define DMD_SZ 2
/*******************************************************************/
/* TIMER REGISTER ADDRESSES (TIM0 = Timer 0, TIM1 = Timer 1 */
/* Defined for all devices */
/*******************************************************************/
#define TIM_ADDR(port) (port ? 0x30 : 0x24)
#define TIM(port) *(volatile unsigned int*)TIM_ADDR(port)
#define PRD_ADDR(port) (port ? 0x31 : 0x25)
#define PRD(port) *(volatile unsigned int*)PRD_ADDR(port)
#define TCR_ADDR(port) (port ? 0x32 : 0x26)
#define TCR(port) *(volatile unsigned int*)TCR_ADDR(port)
/*********************************************************************/
/* EXTERNAL BUS CONTROL REGISTERS */
/*********************************************************************/
#define BSCR *(volatile unsigned int*)0x29
#define BSCR_ADDR 0x29
#define SWCR *(volatile unsigned int*)0x2B
#define SWCR_ADDR 0x2B
#define SWWSR *(volatile unsigned int*)0x28
#define SWWSR_ADDR 0x28
/*********************************************************************/
/* HOST PORT INTERFACE REGISTER ADDRESS */
/* Defined for C54XX */
/*********************************************************************/
#define HPIC *(volatile unsigned int*)0x2C
#define HPIC_ADDR 0x2C
#define HPI_ADDR 0x1000
/*********************************************************************/
/* Defined flags for use in setting control for HPI host interface */
/* control pins */
/* The value of these constants is their relative bit position in */
/* the control structure for the host side of the HPI interface */
/*********************************************************************/
#define HAS_PIN 0
#define HBIL_PIN 1
#define HCNTL0_PIN 2
#define HCNTL1_PIN 3
#define HCS_PIN 4
#define HD0_PIN 5
#define HDS1_PIN 6
#define HDS2_PIN 7
#define HINT_PIN 8
#define HRDY_PIN 9
#define HRW_PIN 10
/*********************************************************************/
/* CLOCK MODE REGISTER ADDRESS */
/* Defined for C54XX */
/*********************************************************************/
#define CLKMD *(volatile unsigned int*)0x58
#define CLKMD_ADDR 0x58
/*********************************************************************/
/* Extended Program Counter -XPC register */
/*********************************************************************/
extern volatile unsigned int XPC;
#define XPC *(volatile unsigned int*)0x1e
#define XPC_ADDR 0x1e
/*********************************************************************/
/* Program Control and Status Registers (PMST, ST0, ST1) */
/*********************************************************************/
#define PMST *(volatile unsigned int*)0x1d
#define PMST_ADDR 0x1d
#define ST0 *(volatile unsigned int*)0x06
#define ST0_ADDR 0x06
#define ST1 *(volatile unsigned int*)0x07
#define ST1_ADDR 0x07
/*********************************************************************/
/* General-purpose I/O pins control registers (GPIOCR, GPIOSR) */
/*********************************************************************/
#define GPIOCR *(volatile unsigned int*)0x3C
#define GPIOCR_ADDR 0x3C
#define GPIOSR *(volatile unsigned int*)0x3D
#define GPIOSR_ADDR 0x3D
#define __54XXREGS
#endif
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