📄 linux-libc-headers-2.6.8-cleanup.patch
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#define HPC3_ERXCTRL_STAT7 0x00000080 /* Rdonlt old/new status bit from Seeq */@@ -125,15 +125,15 @@ #define HPC3_ERXCTRL_AMASK 0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */ #define HPC3_ERXCTRL_RBO 0x00000800 /* Receive buffer overflow if set to 1 */ - volatile u32 rx_gfptr; /* current GIO fifo ptr */- volatile u32 rx_dfptr; /* current device fifo ptr */- u32 _unused1; /* padding */- volatile u32 rx_reset; /* reset register */+ volatile __u32 rx_gfptr; /* current GIO fifo ptr */+ volatile __u32 rx_dfptr; /* current device fifo ptr */+ __u32 _unused1; /* padding */+ volatile __u32 rx_reset; /* reset register */ #define HPC3_ERXRST_CRESET 0x1 /* Reset dma channel and external controller */ #define HPC3_ERXRST_CLRIRQ 0x2 /* Clear channel interrupt */ #define HPC3_ERXRST_LBACK 0x4 /* Enable diagnostic loopback mode of Seeq8003 */ - volatile u32 rx_dconfig; /* DMA configuration register */+ volatile __u32 rx_dconfig; /* DMA configuration register */ #define HPC3_ERXDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */ #define HPC3_ERXDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */ #define HPC3_ERXDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */@@ -143,26 +143,26 @@ #define HPC3_ERXDCFG_FIRQ 0x08000 /* Another bad packet timeout enable */ #define HPC3_ERXDCFG_PTO 0x30000 /* Programmed timeout value for above two */ - volatile u32 rx_pconfig; /* PIO configuration register */+ volatile __u32 rx_pconfig; /* PIO configuration register */ #define HPC3_ERXPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */ #define HPC3_ERXPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */ #define HPC3_ERXPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */ #define HPC3_ERXPCFG_TST 0x1000 /* Diagnistic ram test feature bit */ - u32 _unused2[0x1000/4 - 8]; /* padding */+ __u32 _unused2[0x1000/4 - 8]; /* padding */ /* Transmitter registers. */- volatile u32 tx_cbptr; /* current dma buffer ptr, diagnostic use only */- volatile u32 tx_ndptr; /* next dma descriptor ptr */- u32 _unused3[0x1000/4 - 2]; /* padding */- volatile u32 tx_bcd; /* byte count info */+ volatile __u32 tx_cbptr; /* current dma buffer ptr, diagnostic use only */+ volatile __u32 tx_ndptr; /* next dma descriptor ptr */+ __u32 _unused3[0x1000/4 - 2]; /* padding */+ volatile __u32 tx_bcd; /* byte count info */ #define HPC3_ETXBCD_BCNTMSK 0x00003fff /* bytes to be read from memory */ #define HPC3_ETXBCD_ESAMP 0x10000000 /* if set, too late to add descriptor */ #define HPC3_ETXBCD_XIE 0x20000000 /* Interrupt cpu at end of cur desc */ #define HPC3_ETXBCD_EOP 0x40000000 /* Last byte of cur buf is end of packet */ #define HPC3_ETXBCD_EOX 0x80000000 /* This buf is the end of desc chain */ - volatile u32 tx_ctrl; /* control register */+ volatile __u32 tx_ctrl; /* control register */ #define HPC3_ETXCTRL_STAT30 0x0000000f /* Rdonly copy of seeq tx stat reg */ #define HPC3_ETXCTRL_STAT4 0x00000010 /* Indicate late collision occurred */ #define HPC3_ETXCTRL_STAT75 0x000000e0 /* Rdonly irq status from seeq */@@ -170,9 +170,9 @@ #define HPC3_ETXCTRL_ACTIVE 0x00000200 /* DMA tx channel is active */ #define HPC3_ETXCTRL_AMASK 0x00000400 /* Indicates ACTIVE inhibits PIO's */ - volatile u32 tx_gfptr; /* current GIO fifo ptr */- volatile u32 tx_dfptr; /* current device fifo ptr */- u32 _unused4[0x1000/4 - 4]; /* padding */+ volatile __u32 tx_gfptr; /* current GIO fifo ptr */+ volatile __u32 tx_dfptr; /* current device fifo ptr */+ __u32 _unused4[0x1000/4 - 4]; /* padding */ }; struct hpc3_regs {@@ -188,7 +188,7 @@ /* Here are where the hpc3 fifo's can be directly accessed * via PIO accesses. Under normal operation we never stick * our grubby paws in here so it's just padding. */- u32 _unused0[0x18000/4];+ __u32 _unused0[0x18000/4]; /* HPC3 irq status regs. Due to a peculiar bug you need to * look at two different register addresses to get at all of@@ -197,42 +197,42 @@ * reliably report bits 9:5 of the hpc3 irq status. I told * you it was a peculiar bug. ;-) */- volatile u32 istat0; /* Irq status, only bits <4:0> reliable. */+ volatile __u32 istat0; /* Irq status, only bits <4:0> reliable. */ #define HPC3_ISTAT_PBIMASK 0x0ff /* irq bits for pbus devs 0 --> 7 */ #define HPC3_ISTAT_SC0MASK 0x100 /* irq bit for scsi channel 0 */ #define HPC3_ISTAT_SC1MASK 0x200 /* irq bit for scsi channel 1 */ - volatile u32 gio_misc; /* GIO misc control bits. */+ volatile __u32 gio_misc; /* GIO misc control bits. */ #define HPC3_GIOMISC_ERTIME 0x1 /* Enable external timer real time. */ #define HPC3_GIOMISC_DENDIAN 0x2 /* dma descriptor endian, 1=lit 0=big */ - volatile u32 eeprom; /* EEPROM data reg. */+ volatile __u32 eeprom; /* EEPROM data reg. */ #define HPC3_EEPROM_EPROT 0x01 /* Protect register enable */ #define HPC3_EEPROM_CSEL 0x02 /* Chip select */ #define HPC3_EEPROM_ECLK 0x04 /* EEPROM clock */ #define HPC3_EEPROM_DATO 0x08 /* Data out */ #define HPC3_EEPROM_DATI 0x10 /* Data in */ - volatile u32 istat1; /* Irq status, only bits <9:5> reliable. */- volatile u32 bestat; /* Bus error interrupt status reg. */+ volatile __u32 istat1; /* Irq status, only bits <9:5> reliable. */+ volatile __u32 bestat; /* Bus error interrupt status reg. */ #define HPC3_BESTAT_BLMASK 0x000ff /* Bus lane where bad parity occurred */ #define HPC3_BESTAT_CTYPE 0x00100 /* Bus cycle type, 0=PIO 1=DMA */ #define HPC3_BESTAT_PIDSHIFT 9 #define HPC3_BESTAT_PIDMASK 0x3f700 /* DMA channel parity identifier */ - u32 _unused1[0x14000/4 - 5]; /* padding */+ __u32 _unused1[0x14000/4 - 5]; /* padding */ /* Now direct PIO per-HPC3 peripheral access to external regs. */- volatile u32 scsi0_ext[256]; /* SCSI channel 0 external regs */- u32 _unused2[0x7c00/4];- volatile u32 scsi1_ext[256]; /* SCSI channel 1 external regs */- u32 _unused3[0x7c00/4];- volatile u32 eth_ext[320]; /* Ethernet external registers */- u32 _unused4[0x3b00/4];+ volatile __u32 scsi0_ext[256]; /* SCSI channel 0 external regs */+ __u32 _unused2[0x7c00/4];+ volatile __u32 scsi1_ext[256]; /* SCSI channel 1 external regs */+ __u32 _unused3[0x7c00/4];+ volatile __u32 eth_ext[320]; /* Ethernet external registers */+ __u32 _unused4[0x3b00/4]; /* Per-peripheral device external registers and DMA/PIO control. */- volatile u32 pbus_extregs[16][256];- volatile u32 pbus_dmacfg[8][128];+ volatile __u32 pbus_extregs[16][256];+ volatile __u32 pbus_dmacfg[8][128]; /* Cycles to spend in D3 for reads */ #define HPC3_DMACFG_D3R_MASK 0x00000001 #define HPC3_DMACFG_D3R_SHIFT 0@@ -262,7 +262,7 @@ #define HPC3_DMACFG_BURST_SHIFT 22 /* Use live pbus_dreq unsynchronized signal */ #define HPC3_DMACFG_DRQLIVE 0x08000000- volatile u32 pbus_piocfg[16][64];+ volatile __u32 pbus_piocfg[16][64]; /* Cycles to spend in P2 state for reads */ #define HPC3_PIOCFG_P2R_MASK 0x00001 #define HPC3_PIOCFG_P2R_SHIFT 0@@ -287,21 +287,21 @@ #define HPC3_PIOCFG_EVENHI 0x80000 /* PBUS PROM control regs. */- volatile u32 pbus_promwe; /* PROM write enable register */+ volatile __u32 pbus_promwe; /* PROM write enable register */ #define HPC3_PROM_WENAB 0x1 /* Enable writes to the PROM */ - u32 _unused5[0x0800/4 - 1];- volatile u32 pbus_promswap; /* Chip select swap reg */+ __u32 _unused5[0x0800/4 - 1];+ volatile __u32 pbus_promswap; /* Chip select swap reg */ #define HPC3_PROM_SWAP 0x1 /* invert GIO addr bit to select prom0 or prom1 */ - u32 _unused6[0x0800/4 - 1];- volatile u32 pbus_gout; /* PROM general purpose output reg */+ __u32 _unused6[0x0800/4 - 1];+ volatile __u32 pbus_gout; /* PROM general purpose output reg */ #define HPC3_PROM_STAT 0x1 /* General purpose status bit in gout */ - u32 _unused7[0x1000/4 - 1];- volatile u32 rtcregs[14]; /* Dallas clock registers */- u32 _unused8[50];- volatile u32 bbram[8192-50-14]; /* Battery backed ram */+ __u32 _unused7[0x1000/4 - 1];+ volatile __u32 rtcregs[14]; /* Dallas clock registers */+ __u32 _unused8[50];+ volatile __u32 bbram[8192-50-14]; /* Battery backed ram */ }; /* diff -urN linux-libc-headers-2.6.8.0-dist/include/asm-mips/sgi/ioc.h linux-libc-headers-2.6.8.0/include/asm-mips/sgi/ioc.h--- linux-libc-headers-2.6.8.0-dist/include/asm-mips/sgi/ioc.h 2004-03-28 07:51:54.000000000 -0600+++ linux-libc-headers-2.6.8.0/include/asm-mips/sgi/ioc.h 2004-08-26 05:24:48.000000000 -0500@@ -22,26 +22,26 @@ */ struct sgioc_uart_regs {- u8 _ctrl1[3];- volatile u8 ctrl1;- u8 _data1[3];- volatile u8 data1;- u8 _ctrl2[3];- volatile u8 ctrl2;- u8 _data2[3];- volatile u8 data2;+ __u8 _ctrl1[3];+ volatile __u8 ctrl1;+ __u8 _data1[3];+ volatile __u8 data1;+ __u8 _ctrl2[3];+ volatile __u8 ctrl2;+ __u8 _data2[3];+ volatile __u8 data2; }; struct sgioc_keyb_regs {- u8 _data[3];- volatile u8 data;- u8 _command[3];- volatile u8 command;+ __u8 _data[3];+ volatile __u8 data;+ __u8 _command[3];+ volatile __u8 command; }; struct sgint_regs {- u8 _istat0[3];- volatile u8 istat0; /* Interrupt status zero */+ __u8 _istat0[3];+ volatile __u8 istat0; /* Interrupt status zero */ #define SGINT_ISTAT0_FFULL 0x01 #define SGINT_ISTAT0_SCSI0 0x02 #define SGINT_ISTAT0_SCSI1 0x04@@ -50,10 +50,10 @@ #define SGINT_ISTAT0_PPORT 0x20 #define SGINT_ISTAT0_HPC2 0x40 #define SGINT_ISTAT0_LIO2 0x80- u8 _imask0[3];- volatile u8 imask0; /* Interrupt mask zero */- u8 _istat1[3];- volatile u8 istat1; /* Interrupt status one */+ __u8 _imask0[3];+ volatile __u8 imask0; /* Interrupt mask zero */+ __u8 _istat1[3];+ volatile __u8 istat1; /* Interrupt status one */ #define SGINT_ISTAT1_ISDNI 0x01 #define SGINT_ISTAT1_PWR 0x02 #define SGINT_ISTAT1_ISDNH 0x04@@ -62,29 +62,29 @@ #define SGINT_ISTAT1_AFAIL 0x20 #define SGINT_ISTAT1_VIDEO 0x40 #define SGINT_ISTAT1_GIO2 0x80- u8 _imask1[3];- volatile u8 imask1; /* Interrupt mask one */- u8 _vmeistat[3];- volatile u8 vmeistat; /* VME interrupt status */- u8 _cmeimask0[3];- volatile u8 cmeimask0; /* VME interrupt mask zero */- u8 _cmeimask1[3];- volatile u8 cmeimask1; /* VME interrupt mask one */- u8 _cmepol[3];- volatile u8 cmepol; /* VME polarity */- u8 _tclear[3];- volatile u8 tclear;- u8 _errstat[3];- volatile u8 errstat; /* Error status reg, reserved on INT2 */- u32 _unused0[2];- u8 _tcnt0[3];- volatile u8 tcnt0; /* counter 0 */- u8 _tcnt1[3];- volatile u8 tcnt1; /* counter 1 */- u8 _tcnt2[3];- volatile u8 tcnt2; /* counter 2 */- u8 _tcword[3];- volatile u8 tcword; /* control word */+ __u8 _imask1[3];+ volatile __u8 imask1; /* Interrupt mask one */+ __u8 _vmeistat[3];+ volatile __u8 vmeistat; /* VME interrupt status */+ __u8 _cmeimask0[3];+ volatile __u8 cmeimask0; /* VME interrupt mask zero */+ __u8 _cmeimask1[3];+ volatile __u8 cmeimask1; /* VME interrupt mask one */+ __u8 _cmepol[3];+ volatile __u8 cmepol; /* VME polarity */+ __u8 _tclear[3];+ volatile __u8 tclear;+ __u8 _errstat[3];+ volatile __u8 errstat; /* Error status reg, reserved on INT2 */+ __u32 _unused0[2];+ __u8 _tcnt0[3];+ volatile __u8 tcnt0; /* counter 0 */+ __u8 _tcnt1[3];+ volatile __u8 tcnt1; /* counter 1 */+ __u8 _tcnt2[3];+ volatile __u8 tcnt2; /* counter 2 */+ __u8 _tcword[3];+ volatile __u8 tcword; /* control word */ #define SGINT_TCWORD_BCD 0x01 /* Use BCD mode for counters */ #define SGINT_TCWORD_MMASK 0x0e /* Mode bitmask. */ #define SGINT_TCWORD_MITC 0x00 /* IRQ on terminal count (doesn't work) */@@ -115,55 +115,55 @@ #define SGINT_TCSAMP_COUNTER ((SGINT_TIMER_CLOCK / HZ) + 255) /* We need software copies of these because they are write only. */-extern u8 sgi_ioc_reset, sgi_ioc_write;+extern __u8 sgi_ioc_reset, sgi_ioc_write; struct sgioc_regs { struct pi1_regs pport;- u32 _unused0[2];+ __u32 _unused0[2]; struct sgioc_uart_regs serport; struct sgioc_keyb_regs kbdmouse;- u8 _gcsel[3];- volatile u8 gcsel;- u8 _genctrl[3];- volatile u8 genctrl;- u8 _panel[3];- volatile u8 panel;+ __u8 _gcsel[3];+ volatile __u8 gcsel;+ __u8 _genctrl[3];+ volatile __u8 genctrl;+ __u8 _panel[3];+ volatile __u8 panel; #define SGIOC_PANEL_POWERON 0x01 #define SGIOC_PANEL_POWERINTR 0x02 #define SGIOC_PANEL_VOLDNINTR 0x10 #define SGIOC_PANEL_VOLDNHOLD 0x20 #define SGIOC_PANEL_VOLUPINTR 0x40 #define SGIOC_PANEL_VOLUPHOLD 0x80- u32 _unused1;- u8 _sysid[3];- volatile u8 sysid;+ __u32 _unused1;+ __u8 _sysid[3];+ volatile __u8 sysid; #define SGIOC_SYSID_FULLHOUSE 0x01 #define SGIOC_SYSID_BOARDREV(x) ((x & 0xe0) > 5) #define SGIOC_SYSID_CHIPREV(x) ((x & 0x1e) > 1)- u32 _unused2;- u8 _read[3];- volatile u8 read;- u32 _unused3;- u8 _dmasel[3];- volatile u8 dmasel;+ __u32 _unused2;+ __u8 _read[3];+ volatile __u8 read;+ __u32 _unused3;+ __u8 _dmasel[3];+ volatile __u8 dmasel; #define SGIOC_DMASEL_SCLK10MHZ 0x00 /* use 10MHZ serial clock */ #define SGIOC_DMASEL_ISDNB 0x01 /* enable isdn B */ #define SGIOC_DMASEL_ISDNA 0x02 /* enable isdn A */ #define SGIOC_DMASEL_PPORT 0x04 /* use parallel DMA */ #define SGIOC_DMASEL_SCLK667MHZ 0x10 /* use 6.67MHZ serial clock */ #define SGIOC_DMASEL_SCLKEXT 0x20 /* use external serial clock */- u32 _unused4;- u8 _reset[3];- volatile u8 reset;+ __u32 _unused4;+ __u8 _reset[3];+ volatile __u8 reset; #define SGIOC_RESET_PPORT 0x01 /* 0=parport reset, 1=nornal */ #define SGIOC_RESET_KBDMOUSE 0x02 /* 0=kbdmouse reset, 1=normal */ #define SGIOC_RESET_EISA 0x04 /* 0=eisa reset, 1=normal */ #define SGIOC_RESET_ISDN 0x08 /* 0=isdn reset, 1=normal */ #define SGIOC_RESET_LC0OFF 0x10 /* guiness: turn led off (red, else green) */ #define SGIOC_RESET_LC1OFF 0x20 /* guiness: turn led off (green, else amber) */- u32 _unused5;- u8 _write[3];- volatile u8 write;+ __u32 _unused5;+ __u8 _write[3];+ volatile __u8 write; #define SGIOC_WRITE_NTHRESH 0x01 /*⌨️ 快捷键说明
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