linux-libc-headers-2.6.8-cleanup.patch

最新的文件系统生成工具

+		__u16	s[8 / 2];
+		__u32	l[8 / 4];
+		__u64	d[8 / 8];
 	} b_pci_iack;						/* 0x030000 */
 
-	u8	_pad_030007[0x04fff8];			/* 0x030008-0x07FFFF */
+	__u8	_pad_030007[0x04fff8];			/* 0x030008-0x07FFFF */
 
 	/* External Address Translation Entry RAM 0x080000-0x0FFFFF */
 	bridge_ate_t    b_ext_ate_ram[0x10000];
@@ -239,10 +239,10 @@
 
 	/* PCI/GIO Device Spaces 0x200000-0xBFFFFF */
 	union {				/* make all access sizes available. */
-		u8	c[0x100000 / 1];
-		u16	s[0x100000 / 2];
-		u32	l[0x100000 / 4];
-		u64	d[0x100000 / 8];
+		__u8	c[0x100000 / 1];
+		__u16	s[0x100000 / 2];
+		__u32	l[0x100000 / 4];
+		__u64	d[0x100000 / 8];
 	} b_devio_raw[10];				/* 0x200000 */
 
 	/* b_devio macro is a bit strange; it reflects the
@@ -253,10 +253,10 @@
 
 	/* External Flash Proms 1,0 0xC00000-0xFFFFFF */
 	union {		/* make all access sizes available. */
-		u8	c[0x400000 / 1];	/* read-only */
-		u16	s[0x400000 / 2];	/* read-write */
-		u32	l[0x400000 / 4];	/* read-only */
-		u64	d[0x400000 / 8];	/* read-only */
+		__u8	c[0x400000 / 1];	/* read-only */
+		__u16	s[0x400000 / 2];	/* read-write */
+		__u32	l[0x400000 / 4];	/* read-only */
+		__u64	d[0x400000 / 8];	/* read-only */
 	} b_external_flash;			/* 0xC00000 */
 } bridge_t;
 
@@ -266,9 +266,9 @@
  */
 typedef struct bridge_err_cmdword_s {
 	union {
-		u32		cmd_word;
+		__u32		cmd_word;
 		struct {
-			u32	didn:4,		/* Destination ID */
+			__u32	didn:4,		/* Destination ID */
 				sidn:4,		/* Source ID	  */
 				pactyp:4,	/* Packet type	  */
 				tnum:5,		/* Trans Number	  */
@@ -799,17 +799,17 @@
 #ifndef __ASSEMBLY__
 /* Address translation entry for mapped pci32 accesses */
 typedef union ate_u {
-	u64	ent;
+	__u64	ent;
 	struct ate_s {
-		u64	rmf:16;
-		u64	addr:36;
-		u64	targ:4;
-		u64	reserved:3;
-		u64	barrier:1;
-		u64	prefetch:1;
-		u64	precise:1;
-		u64	coherent:1;
-		u64	valid:1;
+		__u64	rmf:16;
+		__u64	addr:36;
+		__u64	targ:4;
+		__u64	reserved:3;
+		__u64	barrier:1;
+		__u64	prefetch:1;
+		__u64	precise:1;
+		__u64	coherent:1;
+		__u64	valid:1;
 	} field;
 } ate_t;
 #endif /* !__ASSEMBLY__ */
diff -urN linux-libc-headers-2.6.8.0-dist/include/asm-mips/pci_channel.h linux-libc-headers-2.6.8.0/include/asm-mips/pci_channel.h
--- linux-libc-headers-2.6.8.0-dist/include/asm-mips/pci_channel.h	2004-03-28 07:51:52.000000000 -0600
+++ linux-libc-headers-2.6.8.0/include/asm-mips/pci_channel.h	2004-08-26 05:21:47.000000000 -0500
@@ -41,6 +41,6 @@
 /*
  * board supplied pci irq fixup routine
  */
-extern int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
+extern int pcibios_map_irq(struct pci_dev *dev, __u8 slot, __u8 pin);
 
 #endif  /* __ASM_PCI_CHANNEL_H */
diff -urN linux-libc-headers-2.6.8.0-dist/include/asm-mips/pgalloc.h linux-libc-headers-2.6.8.0/include/asm-mips/pgalloc.h
--- linux-libc-headers-2.6.8.0-dist/include/asm-mips/pgalloc.h	2004-06-09 07:00:41.000000000 -0500
+++ linux-libc-headers-2.6.8.0/include/asm-mips/pgalloc.h	2004-08-26 05:14:41.000000000 -0500
@@ -85,7 +85,7 @@
 
 #define __pte_free_tlb(tlb,pte)		tlb_remove_page((tlb),(pte))
 
-#ifdef CONFIG_MIPS32
+#ifndef __mips64
 #define pgd_populate(mm, pmd, pte)	BUG()
 
 /*
@@ -97,7 +97,7 @@
 #define __pmd_free_tlb(tlb,x)		do { } while (0)
 #endif
 
-#ifdef CONFIG_MIPS64
+#ifdef __mips64
 
 #define pgd_populate(mm, pgd, pmd)	set_pgd(pgd, __pgd(pmd))
 
diff -urN linux-libc-headers-2.6.8.0-dist/include/asm-mips/prctl.h linux-libc-headers-2.6.8.0/include/asm-mips/prctl.h
--- linux-libc-headers-2.6.8.0-dist/include/asm-mips/prctl.h	2003-12-15 12:47:02.000000000 -0600
+++ linux-libc-headers-2.6.8.0/include/asm-mips/prctl.h	2004-08-26 05:21:43.000000000 -0500
@@ -12,21 +12,21 @@
 #define PRDA ((struct prda *) PRDA_ADDRESS)
 
 struct prda_sys {
-	pid_t t_pid;
-        u32   t_hint;
-        u32   t_dlactseq;
-        u32   t_fpflags;
-        u32   t_prid;		/* processor type, $prid CP0 register */
-        u32   t_dlendseq;
-        u64   t_unused1[5];
-        pid_t t_rpid;
-        s32   t_resched;
-        u32   t_unused[8];
-        u32   t_cpu;		/* current/last cpu */
+	pid_t   t_pid;
+        __u32   t_hint;
+        __u32   t_dlactseq;
+        __u32   t_fpflags;
+        __u32   t_prid;		/* processor type, $prid CP0 register */
+        __u32   t_dlendseq;
+        __u64   t_unused1[5];
+        pid_t   t_rpid;
+        __s32   t_resched;
+        __u32   t_unused[8];
+        __u32   t_cpu;		/* current/last cpu */
 
 	/* FIXME: The signal information, not supported by Linux now */
-	u32   t_flags;		/* if true, then the sigprocmask is in userspace */
-	u32   t_sigprocmask [1]; /* the sigprocmask */
+	__u32   t_flags;		/* if true, then the sigprocmask is in userspace */
+	__u32   t_sigprocmask [1]; /* the sigprocmask */
 };
 
 struct prda {
diff -urN linux-libc-headers-2.6.8.0-dist/include/asm-mips/processor.h linux-libc-headers-2.6.8.0/include/asm-mips/processor.h
--- linux-libc-headers-2.6.8.0-dist/include/asm-mips/processor.h	2004-08-18 13:15:41.000000000 -0500
+++ linux-libc-headers-2.6.8.0/include/asm-mips/processor.h	2004-08-26 05:23:24.000000000 -0500
@@ -102,7 +102,7 @@
 #define MCA_bus 0
 #define MCA_bus__is_a_macro /* for versions in ksyms.c */
 
-#ifdef CONFIG_MIPS32
+#ifndef __mips64
 /*
  * User space process size: 2GB. This is hardcoded into a few places,
  * so don't change it unless you know what you are doing.
@@ -116,7 +116,7 @@
 #define TASK_UNMAPPED_BASE	(PAGE_ALIGN(TASK_SIZE / 3))
 #endif
 
-#ifdef CONFIG_MIPS64
+#ifdef __mips64
 /*
  * User space process size: 1TB. This is hardcoded into a few places,
  * so don't change it unless you know what you are doing.  TASK_SIZE
@@ -142,7 +142,7 @@
 
 #define NUM_FPU_REGS	32
 
-typedef u64 fpureg_t;
+typedef __u64 fpureg_t;
 
 struct mips_fpu_hard_struct {
 	fpureg_t	fpr[NUM_FPU_REGS];
diff -urN linux-libc-headers-2.6.8.0-dist/include/asm-mips/ptrace.h linux-libc-headers-2.6.8.0/include/asm-mips/ptrace.h
--- linux-libc-headers-2.6.8.0-dist/include/asm-mips/ptrace.h	2004-03-28 07:51:52.000000000 -0600
+++ linux-libc-headers-2.6.8.0/include/asm-mips/ptrace.h	2004-08-26 05:14:41.000000000 -0500
@@ -27,7 +27,7 @@
  * system call/exception. As usual the registers k0/k1 aren't being saved.
  */
 struct pt_regs {
-#ifdef CONFIG_MIPS32
+#ifndef __mips64
 	/* Pad bytes for argument save space on the stack. */
 	unsigned long pad0[6];
 #endif
diff -urN linux-libc-headers-2.6.8.0-dist/include/asm-mips/serial.h linux-libc-headers-2.6.8.0/include/asm-mips/serial.h
--- linux-libc-headers-2.6.8.0-dist/include/asm-mips/serial.h	2004-08-18 13:15:41.000000000 -0500
+++ linux-libc-headers-2.6.8.0/include/asm-mips/serial.h	2004-08-26 13:21:37.000000000 -0500
@@ -68,7 +68,7 @@
 
 #define _JAZZ_SERIAL_INIT(int, base)					\
 	{ .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,	\
-	  .iomem_base = (u8 *) base, .iomem_reg_shift = 0,			\
+	  .iomem_base = (__u8 *) base, .iomem_reg_shift = 0,			\
 	  .io_type = SERIAL_IO_MEM }
 #define JAZZ_SERIAL_PORT_DEFNS						\
 	_JAZZ_SERIAL_INIT(JAZZ_SERIAL1_IRQ, JAZZ_SERIAL1_BASE),		\
@@ -243,7 +243,7 @@
 #define _JAGUAR_ATX_SERIAL_INIT(int, base)				\
 	{ baud_base: JAGUAR_ATX_BASE_BAUD, irq: int,			\
 	  flags: (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),		\
-	  iomem_base: (u8 *) base, iomem_reg_shift: 2,			\
+	  iomem_base: (__u8 *) base, iomem_reg_shift: 2,		\
 	  io_type: SERIAL_IO_MEM }
 #define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS				\
 	_JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE)
@@ -260,7 +260,7 @@
 
 #define _OCELOT_SERIAL_INIT(int, base)					\
 	{ .baud_base = OCELOT_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,	\
-	  .iomem_base = (u8 *) base, .iomem_reg_shift = 2,			\
+	  .iomem_base = (__u8 *) base, .iomem_reg_shift = 2,			\
 	  .io_type = SERIAL_IO_MEM }
 #define MOMENCO_OCELOT_SERIAL_PORT_DEFNS				\
 	_OCELOT_SERIAL_INIT(OCELOT_SERIAL1_IRQ, OCELOT_SERIAL1_BASE)
@@ -281,7 +281,7 @@
 
 #define _OCELOT_G_SERIAL_INIT(int, base)				\
 	{ .baud_base = OCELOT_G_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,\
-	  .iomem_base = (u8 *) base, .iomem_reg_shift = 2,			\
+	  .iomem_base = (__u8 *) base, .iomem_reg_shift = 2,			\
 	  .io_type = SERIAL_IO_MEM }
 #define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS				\
 	_OCELOT_G_SERIAL_INIT(OCELOT_G_SERIAL1_IRQ, OCELOT_G_SERIAL1_BASE)
@@ -303,7 +303,7 @@
 	{ .baud_base		= OCELOT_C_BASE_BAUD,			\
 	  .irq			= (int),				\
 	  .flags		= STD_COM_FLAGS,			\
-	  .iomem_base		= (u8 *) base,				\
+	  .iomem_base		= (__u8 *) base,			\
 	  .iomem_reg_shift	= 2,					\
 	  .io_type		= SERIAL_IO_MEM				\
 	 }
@@ -318,10 +318,10 @@
 #include <asm/ddb5xxx/ddb5477.h>
 #define DDB5477_SERIAL_PORT_DEFNS                                       \
         { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART0, 		\
-	  .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04200, 	\
+	  .flags = STD_COM_FLAGS, .iomem_base = (__u8*)0xbfa04200, 	\
 	  .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM},		\
         { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART1, 		\
-	  .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04240, 	\
+	  .flags = STD_COM_FLAGS, .iomem_base = (__u8*)0xbfa04240, 	\
 	  .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM},
 #else
 #define DDB5477_SERIAL_PORT_DEFNS
diff -urN linux-libc-headers-2.6.8.0-dist/include/asm-mips/sgi/hpc3.h linux-libc-headers-2.6.8.0/include/asm-mips/sgi/hpc3.h
--- linux-libc-headers-2.6.8.0-dist/include/asm-mips/sgi/hpc3.h	2003-12-15 12:47:03.000000000 -0600
+++ linux-libc-headers-2.6.8.0/include/asm-mips/sgi/hpc3.h	2004-08-26 05:24:34.000000000 -0500
@@ -17,8 +17,8 @@
 
 /* An HPC DMA descriptor. */
 struct hpc_dma_desc {
-	u32 pbuf;	/* physical address of data buffer */
-	u32 cntinfo;	/* counter and info bits */
+	__u32 pbuf;	/* physical address of data buffer */
+	__u32 cntinfo;	/* counter and info bits */
 #define HPCDMA_EOX	0x80000000 /* last desc in chain for tx */
 #define HPCDMA_EOR	0x80000000 /* last desc in chain for rx */
 #define HPCDMA_EOXP	0x40000000 /* end of packet for tx */
@@ -30,15 +30,15 @@
 #define HPCDMA_OWN	0x00004000 /* Denotes ring buffer ownership on rx */
 #define HPCDMA_BCNT	0x00003fff /* size in bytes of this dma buffer */
 
-	u32 pnext;	/* paddr of next hpc_dma_desc if any */
+	__u32 pnext;	/* paddr of next hpc_dma_desc if any */
 };
 
 /* The set of regs for each HPC3 PBUS DMA channel. */
 struct hpc3_pbus_dmacregs {
-	volatile u32 pbdma_bptr;	/* pbus dma channel buffer ptr */
-	volatile u32 pbdma_dptr;	/* pbus dma channel desc ptr */
-	u32 _unused0[0x1000/4 - 2];	/* padding */
-	volatile u32 pbdma_ctrl;	/* pbus dma channel control register has
+	volatile __u32 pbdma_bptr;	/* pbus dma channel buffer ptr */
+	volatile __u32 pbdma_dptr;	/* pbus dma channel desc ptr */
+	__u32 _unused0[0x1000/4 - 2];	/* padding */
+	volatile __u32 pbdma_ctrl;	/* pbus dma channel control register has
 					 * copletely different meaning for read
 					 * compared with write */
 	/* read */
@@ -55,20 +55,20 @@
 #define HPC3_PDMACTRL_FB	0x003f0000 /* Ptr to beginning of fifo */
 #define HPC3_PDMACTRL_FE	0x3f000000 /* Ptr to end of fifo */
 
-	u32 _unused1[0x1000/4 - 1];	/* padding */
+	__u32 _unused1[0x1000/4 - 1];	/* padding */
 };
 
 /* The HPC3 SCSI registers, this does not include external ones. */
 struct hpc3_scsiregs {
-	volatile u32 cbptr;	/* current dma buffer ptr, diagnostic use only */
-	volatile u32 ndptr;	/* next dma descriptor ptr */
-	u32 _unused0[0x1000/4 - 2];	/* padding */
-	volatile u32 bcd;	/* byte count info */
+	volatile __u32 cbptr;	/* current dma buffer ptr, diagnostic use only */
+	volatile __u32 ndptr;	/* next dma descriptor ptr */
+	__u32 _unused0[0x1000/4 - 2];	/* padding */
+	volatile __u32 bcd;	/* byte count info */
 #define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */
 #define HPC3_SBCD_XIE     0x00004000 /* Send IRQ when done with cur buf */
 #define HPC3_SBCD_EOX     0x00008000 /* Indicates this is last buf in chain */
 
-	volatile u32 ctrl;    /* control register */
+	volatile __u32 ctrl;    /* control register */
 #define HPC3_SCTRL_IRQ    0x01 /* IRQ asserted, either dma done or parity */
 #define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */
 #define HPC3_SCTRL_DIR    0x04 /* DMA direction, 1=dev2mem 0=mem2dev */
@@ -78,9 +78,9 @@
 #define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */
 #define HPC3_SCTRL_PERR   0x80 /* Bad parity on HPC3 iface to scsi controller */
 
-	volatile u32 gfptr;	/* current GIO fifo ptr */
-	volatile u32 dfptr;	/* current device fifo ptr */
-	volatile u32 dconfig;	/* DMA configuration register */
+	volatile __u32 gfptr;	/* current GIO fifo ptr */
+	volatile __u32 dfptr;	/* current device fifo ptr */
+	volatile __u32 dconfig;	/* DMA configuration register */
 #define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */
 #define HPC3_SDCFG_D1   0x00006 /* Cycles to spend in D1 state */
 #define HPC3_SDCFG_D2   0x00038 /* Cycles to spend in D2 state */
@@ -92,7 +92,7 @@
 #define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */
 #define HPC3_SDCFG_ERLY 0x30000 /* hd_dreq behavior control bits */
 
-	volatile u32 pconfig;	/* PIO configuration register */
+	volatile __u32 pconfig;	/* PIO configuration register */
 #define HPC3_SPCFG_P3   0x0003 /* Cycles to spend in P3 state */
 #define HPC3_SPCFG_P2W  0x001c /* Cycles to spend in P2 state for writes */
 #define HPC3_SPCFG_P2R  0x01e0 /* Cycles to spend in P2 state for reads */
@@ -102,21 +102,21 @@
 #define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */
 #define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */
 
-	u32 _unused1[0x1000/4 - 6];	/* padding */
+	__u32 _unused1[0x1000/4 - 6];	/* padding */
 };
 
 /* SEEQ ethernet HPC3 registers, only one seeq per HPC3. */
 struct hpc3_ethregs {
 	/* Receiver registers. */
-	volatile u32 rx_cbptr;   /* current dma buffer ptr, diagnostic use only */
-	volatile u32 rx_ndptr;   /* next dma descriptor ptr */
-	u32 _unused0[0x1000/4 - 2];	/* padding */
-	volatile u32 rx_bcd;	/* byte count info */
+	volatile __u32 rx_cbptr;   /* current dma buffer ptr, diagnostic use only */
+	volatile __u32 rx_ndptr;   /* next dma descriptor ptr */
+	__u32 _unused0[0x1000/4 - 2];	/* padding */
+	volatile __u32 rx_bcd;	/* byte count info */
 #define HPC3_ERXBCD_BCNTMSK 0x00003fff /* bytes to be sent to memory */
 #define HPC3_ERXBCD_XIE     0x20000000 /* HPC3 interrupts cpu at end of this buf */
 #define HPC3_ERXBCD_EOX     0x80000000 /* flags this as end of descriptor chain */
 
-	volatile u32 rx_ctrl;	/* control register */
+	volatile __u32 rx_ctrl;	/* control register */
 #define HPC3_ERXCTRL_STAT50 0x0000003f /* Receive status reg bits of Seeq8003 */
 #define HPC3_ERXCTRL_STAT6  0x00000040 /* Rdonly irq status */