linux-libc-headers-2.6.8-cleanup.patch

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  * This is used to ensure we don't load something for the wrong architecture.
@@ -150,9 +150,9 @@
  */
 #define ELF_CLASS	ELFCLASS32
 
-#endif /* CONFIG_MIPS32 */
+#endif /* ndef __mips64 */
 
-#ifdef CONFIG_MIPS64
+#ifdef __mips64
 /*
  * This is used to ensure we don't load something for the wrong architecture.
  */
@@ -174,7 +174,7 @@
  */
 #define ELF_CLASS	ELFCLASS64
 
-#endif /* CONFIG_MIPS64 */
+#endif /* __mips64 */
 
 /*
  * These are used to set parameters in the core dumps.
diff -urN linux-libc-headers-2.6.8.0-dist/include/asm-mips/galileo-boards/ev96100.h linux-libc-headers-2.6.8.0/include/asm-mips/galileo-boards/ev96100.h
--- linux-libc-headers-2.6.8.0-dist/include/asm-mips/galileo-boards/ev96100.h	2004-03-28 07:51:53.000000000 -0600
+++ linux-libc-headers-2.6.8.0/include/asm-mips/galileo-boards/ev96100.h	2004-08-26 05:23:12.000000000 -0500
@@ -46,9 +46,9 @@
  * bytes when running bigendian.
  */
 #define __GT_READ(ofs)							\
-	(*(volatile u32 *)(GT64120_BASE+(ofs)))
+	(*(volatile __u32 *)(GT64120_BASE+(ofs)))
 #define __GT_WRITE(ofs, data)						\
-	do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0)
+	do { *(volatile __u32 *)(GT64120_BASE+(ofs)) = (data); } while (0)
 #define GT_READ(ofs)		le32_to_cpu(__GT_READ(ofs))
 #define GT_WRITE(ofs, data)	__GT_WRITE(ofs, cpu_to_le32(data))
 
diff -urN linux-libc-headers-2.6.8.0-dist/include/asm-mips/galileo-boards/gt96100.h linux-libc-headers-2.6.8.0/include/asm-mips/galileo-boards/gt96100.h
--- linux-libc-headers-2.6.8.0-dist/include/asm-mips/galileo-boards/gt96100.h	2004-03-28 07:51:53.000000000 -0600
+++ linux-libc-headers-2.6.8.0/include/asm-mips/galileo-boards/gt96100.h	2004-08-26 05:23:17.000000000 -0500
@@ -27,9 +27,9 @@
 #define MIPS_GT96100_BASE (KSEG1ADDR(0x14000000))
 
 #define GT96100_WRITE(ofs, data) \
-    *(volatile u32 *)(MIPS_GT96100_BASE+ofs) = cpu_to_le32(data)
+    *(volatile __u32 *)(MIPS_GT96100_BASE+ofs) = cpu_to_le32(data)
 #define GT96100_READ(ofs) \
-    le32_to_cpu(*(volatile u32 *)(MIPS_GT96100_BASE+ofs))
+    le32_to_cpu(*(volatile __u32 *)(MIPS_GT96100_BASE+ofs))
 
 #define GT96100_ETH_IO_SIZE 0x4000
 
diff -urN linux-libc-headers-2.6.8.0-dist/include/asm-mips/gt64120.h linux-libc-headers-2.6.8.0/include/asm-mips/gt64120.h
--- linux-libc-headers-2.6.8.0-dist/include/asm-mips/gt64120.h	2004-03-28 07:51:51.000000000 -0600
+++ linux-libc-headers-2.6.8.0/include/asm-mips/gt64120.h	2004-08-26 05:22:36.000000000 -0500
@@ -420,9 +420,9 @@
  * bytes when running bigendian.  We also provide non-swapping versions.
  */
 #define __GT_READ(ofs)							\
-	(*(volatile u32 *)(GT64120_BASE+(ofs)))
+	(*(volatile __u32 *)(GT64120_BASE+(ofs)))
 #define __GT_WRITE(ofs, data)						\
-	do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0)
+	do { *(volatile __u32 *)(GT64120_BASE+(ofs)) = (data); } while (0)
 #define GT_READ(ofs)		le32_to_cpu(__GT_READ(ofs))
 #define GT_WRITE(ofs, data)	__GT_WRITE(ofs, cpu_to_le32(data))
 
diff -urN linux-libc-headers-2.6.8.0-dist/include/asm-mips/io.h linux-libc-headers-2.6.8.0/include/asm-mips/io.h
--- linux-libc-headers-2.6.8.0-dist/include/asm-mips/io.h	2004-03-28 07:51:51.000000000 -0600
+++ linux-libc-headers-2.6.8.0/include/asm-mips/io.h	2004-08-26 05:24:16.000000000 -0500
@@ -173,14 +173,14 @@
 	unsigned long flags)
 {
 	if (cpu_has_64bit_addresses) {
-		u64 base = UNCAC_BASE;
+		__u64 base = UNCAC_BASE;
 
 		/*
 		 * R10000 supports a 2 bit uncached attribute therefore
 		 * UNCAC_BASE may not equal IO_BASE.
 		 */
 		if (flags == _CACHE_UNCACHED)
-			base = (u64) IO_BASE;
+			base = (__u64) IO_BASE;
 		return (void *) (unsigned long) (base + offset);
 	}
 
@@ -245,10 +245,10 @@
 #define __raw_readb(addr)	(*(volatile unsigned char *)(addr))
 #define __raw_readw(addr)	(*(volatile unsigned short *)(addr))
 #define __raw_readl(addr)	(*(volatile unsigned int *)(addr))
-#ifdef CONFIG_MIPS32
+#ifndef __mips64
 #define ____raw_readq(addr)						\
 ({									\
-	u64 __res;							\
+	__u64 __res;							\
 									\
 	__asm__ __volatile__ (						\
 		"	.set	mips3		# ____raw_readq	\n"	\
@@ -263,7 +263,7 @@
 #define __raw_readq(addr)						\
 ({									\
 	unsigned long __flags;						\
-	u64 __res;							\
+	__u64 __res;							\
 									\
 	local_irq_save(__flags);					\
 	__res = ____raw_readq(addr);					\
@@ -271,7 +271,7 @@
 	__res;								\
 })
 #endif
-#ifdef CONFIG_MIPS64
+#ifdef __mips64
 #define ____raw_readq(addr)	(*(volatile unsigned long *)(addr))
 #define __raw_readq(addr)	____raw_readq(addr)
 #endif
@@ -288,10 +288,10 @@
 #define __raw_writeb(b,addr)	((*(volatile unsigned char *)(addr)) = (b))
 #define __raw_writew(w,addr)	((*(volatile unsigned short *)(addr)) = (w))
 #define __raw_writel(l,addr)	((*(volatile unsigned int *)(addr)) = (l))
-#ifdef CONFIG_MIPS32
+#ifndef __mips64
 #define ____raw_writeq(val,addr)						\
 ({									\
-	u64 __tmp;							\
+	__u64 __tmp;							\
 									\
 	__asm__ __volatile__ (						\
 		"	.set	mips3				\n"	\
@@ -313,7 +313,7 @@
 	local_irq_restore(__flags);					\
 })
 #endif
-#ifdef CONFIG_MIPS64
+#ifdef __mips64
 #define ____raw_writeq(q,addr)	((*(volatile unsigned long *)(addr)) = (q))
 #define __raw_writeq(q,addr)	____raw_writeq(q, addr)
 #endif
@@ -400,28 +400,28 @@
 {
 	port = __swizzle_addr_b(port);
 
-	*(volatile u8 *)(mips_io_port_base + port) = __ioswab8(val);
+	*(volatile __u8 *)(mips_io_port_base + port) = __ioswab8(val);
 }
 
 static inline void __outw(unsigned short val, unsigned long port)
 {
 	port = __swizzle_addr_w(port);
 
-	*(volatile u16 *)(mips_io_port_base + port) = __ioswab16(val);
+	*(volatile __u16 *)(mips_io_port_base + port) = __ioswab16(val);
 }
 
 static inline void __outl(unsigned int val, unsigned long port)
 {
 	port = __swizzle_addr_l(port);
 
-	*(volatile u32 *)(mips_io_port_base + port) = __ioswab32(val);
+	*(volatile __u32 *)(mips_io_port_base + port) = __ioswab32(val);
 }
 
 static inline void __outb_p(unsigned char val, unsigned long port)
 {
 	port = __swizzle_addr_b(port);
 
-	*(volatile u8 *)(mips_io_port_base + port) = __ioswab8(val);
+	*(volatile __u8 *)(mips_io_port_base + port) = __ioswab8(val);
 	SLOW_DOWN_IO;
 }
 
@@ -429,7 +429,7 @@
 {
 	port = __swizzle_addr_w(port);
 
-	*(volatile u16 *)(mips_io_port_base + port) = __ioswab16(val);
+	*(volatile __u16 *)(mips_io_port_base + port) = __ioswab16(val);
 	SLOW_DOWN_IO;
 }
 
@@ -437,7 +437,7 @@
 {
 	port = __swizzle_addr_l(port);
 
-	*(volatile u32 *)(mips_io_port_base + port) = __ioswab32(val);
+	*(volatile __u32 *)(mips_io_port_base + port) = __ioswab32(val);
 	SLOW_DOWN_IO;
 }
 
@@ -452,30 +452,30 @@
 {
 	port = __swizzle_addr_b(port);
 
-	return __ioswab8(*(volatile u8 *)(mips_io_port_base + port));
+	return __ioswab8(*(volatile __u8 *)(mips_io_port_base + port));
 }
 
 static inline unsigned short __inw(unsigned long port)
 {
 	port = __swizzle_addr_w(port);
 
-	return __ioswab16(*(volatile u16 *)(mips_io_port_base + port));
+	return __ioswab16(*(volatile __u16 *)(mips_io_port_base + port));
 }
 
 static inline unsigned int __inl(unsigned long port)
 {
 	port = __swizzle_addr_l(port);
 
-	return __ioswab32(*(volatile u32 *)(mips_io_port_base + port));
+	return __ioswab32(*(volatile __u32 *)(mips_io_port_base + port));
 }
 
 static inline unsigned char __inb_p(unsigned long port)
 {
-	u8 __val;
+	__u8 __val;
 
 	port = __swizzle_addr_b(port);
 
-	__val = *(volatile u8 *)(mips_io_port_base + port);
+	__val = *(volatile __u8 *)(mips_io_port_base + port);
 	SLOW_DOWN_IO;
 
 	return __ioswab8(__val);
@@ -483,11 +483,11 @@
 
 static inline unsigned short __inw_p(unsigned long port)
 {
-	u16 __val;
+	__u16 __val;
 
 	port = __swizzle_addr_w(port);
 
-	__val = *(volatile u16 *)(mips_io_port_base + port);
+	__val = *(volatile __u16 *)(mips_io_port_base + port);
 	SLOW_DOWN_IO;
 
 	return __ioswab16(__val);
@@ -495,11 +495,11 @@
 
 static inline unsigned int __inl_p(unsigned long port)
 {
-	u32 __val;
+	__u32 __val;
 
 	port = __swizzle_addr_l(port);
 
-	__val = *(volatile u32 *)(mips_io_port_base + port);
+	__val = *(volatile __u32 *)(mips_io_port_base + port);
 	SLOW_DOWN_IO;
 
 	return __ioswab32(__val);
@@ -515,7 +515,7 @@
 static inline void __outsb(unsigned long port, void *addr, unsigned int count)
 {
 	while (count--) {
-		outb(*(u8 *)addr, port);
+		outb(*(__u8 *)addr, port);
 		addr++;
 	}
 }
@@ -523,7 +523,7 @@
 static inline void __insb(unsigned long port, void *addr, unsigned int count)
 {
 	while (count--) {
-		*(u8 *)addr = inb(port);
+		*(__u8 *)addr = inb(port);
 		addr++;
 	}
 }
@@ -531,7 +531,7 @@
 static inline void __outsw(unsigned long port, void *addr, unsigned int count)
 {
 	while (count--) {
-		outw(*(u16 *)addr, port);
+		outw(*(__u16 *)addr, port);
 		addr += 2;
 	}
 }
@@ -539,7 +539,7 @@
 static inline void __insw(unsigned long port, void *addr, unsigned int count)
 {
 	while (count--) {
-		*(u16 *)addr = inw(port);
+		*(__u16 *)addr = inw(port);
 		addr += 2;
 	}
 }
@@ -547,7 +547,7 @@
 static inline void __outsl(unsigned long port, void *addr, unsigned int count)
 {
 	while (count--) {
-		outl(*(u32 *)addr, port);
+		outl(*(__u32 *)addr, port);
 		addr += 4;
 	}
 }
@@ -555,7 +555,7 @@
 static inline void __insl(unsigned long port, void *addr, unsigned int count)
 {
 	while (count--) {
-		*(u32 *)addr = inl(port);
+		*(__u32 *)addr = inl(port);
 		addr += 4;
 	}
 }
@@ -617,7 +617,7 @@
 #define __CSR_32_ADJUST 0
 #endif
 
-#define csr_out32(v,a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
-#define csr_in32(a)    (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
+#define csr_out32(v,a) (*(volatile __u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
+#define csr_in32(a)    (*(volatile __u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
 
 #endif /* _ASM_IO_H */
diff -urN linux-libc-headers-2.6.8.0-dist/include/asm-mips/ip32/mace.h linux-libc-headers-2.6.8.0/include/asm-mips/ip32/mace.h
--- linux-libc-headers-2.6.8.0-dist/include/asm-mips/ip32/mace.h	2004-06-09 07:00:41.000000000 -0500
+++ linux-libc-headers-2.6.8.0/include/asm-mips/ip32/mace.h	2004-08-26 05:14:41.000000000 -0500
@@ -22,7 +22,7 @@
 #undef BIT
 #define BIT(x) (1ULL << (x))
 
-#ifdef CONFIG_MIPS32
+#ifndef __mips64
 typedef struct {
 	volatile unsigned long long reg;
 } mace64_t;
@@ -32,7 +32,7 @@
 	volatile unsigned long reg;
 } mace32_t;
 #endif
-#ifdef CONFIG_MIPS64
+#ifdef __mips64
 typedef struct {
 	volatile unsigned long reg;
 } mace64_t;
diff -urN linux-libc-headers-2.6.8.0-dist/include/asm-mips/it8172/it8172.h linux-libc-headers-2.6.8.0/include/asm-mips/it8172/it8172.h
--- linux-libc-headers-2.6.8.0-dist/include/asm-mips/it8172/it8172.h	2003-12-15 12:47:03.000000000 -0600
+++ linux-libc-headers-2.6.8.0/include/asm-mips/it8172/it8172.h	2004-08-26 05:22:54.000000000 -0500
@@ -336,13 +336,13 @@
 #define TIMER_TIDR				0x0E
 
 
-#define IT_WRITE(ofs, data) *(volatile u32 *)KSEG1ADDR((IT8172_BASE+ofs)) = data
-#define IT_READ(ofs, data)  data = *(volatile u32 *)KSEG1ADDR((IT8172_BASE+ofs))
+#define IT_WRITE(ofs, data) *(volatile __u32 *)KSEG1ADDR((IT8172_BASE+ofs)) = data
+#define IT_READ(ofs, data)  data = *(volatile __u32 *)KSEG1ADDR((IT8172_BASE+ofs))
 
-#define IT_IO_WRITE(ofs, data) *(volatile u32 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) = data
-#define IT_IO_READ(ofs, data)  data = *(volatile u32 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs))
+#define IT_IO_WRITE(ofs, data) *(volatile __u32 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) = data
+#define IT_IO_READ(ofs, data)  data = *(volatile __u32 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs))
 
-#define IT_IO_WRITE16(ofs, data) *(volatile u16 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) = data
-#define IT_IO_READ16(ofs, data)  data = *(volatile u16 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs))
+#define IT_IO_WRITE16(ofs, data) *(volatile __u16 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) = data
+#define IT_IO_READ16(ofs, data)  data = *(volatile __u16 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs))
 
 #endif
diff -urN linux-libc-headers-2.6.8.0-dist/include/asm-mips/lasat/head.h linux-libc-headers-2.6.8.0/include/asm-mips/lasat/head.h