ad1881_registers.h

ADSP-21160下的数字带通滤波器实现的汇编代码。 开发环境为 Visual Dsp 4.5++。

/* Codec register initializations */
/* Refer to AD1881 Data Sheet for register bit assignments */
#define	Select_LINE_INPUT	0x0404		/* LINE IN - 0X0404, Mic In - 0x0000 */
#define Select_MIC_INPUT	0x0000
#define Line_Level_Volume	0x0000		/* 0 dB for line inputs */
#define Mic_Level_Volume	0x0F0F
#define	Sample_Rate			23456
#define	Sample_Rate2		48000
#define Fs_Reverb 			29761		/* Sample Rate is 29761 Hz, default recommended by Dattorro */
										/* reducing Fs will reduce delay line memory requirements */
										/* Reverberation can be convincing at sample rates as low as 20-24 kHz */

/* AD1881 TDM Timeslot Definitions */
#define		TAG_PHASE				0
#define		COMMAND_ADDRESS_SLOT	1
#define		COMMAND_DATA_SLOT		2
#define		STATUS_ADDRESS_SLOT		1
#define		STATUS_DATA_SLOT		2
#define		LEFT					3
#define		RIGHT					4

/* Left and Right ADC valid Bits used for testing of valid audio data in current TDM frame */
#define		M_Left_ADC				12
#define		M_Right_ADC				11
#define		DAC_Req_Left			0x80
#define		DAC_Req_Right			0x40


/* AD1881 Codec Register Address Definitions */
#define		REGS_RESET				0x0000
#define		MASTER_VOLUME			0x0200
#define		RESERVED_REG_1			0x0400
#define		MASTER_VOLUME_MONO		0x0600	
#define		RESERVED_REG_2			0x0800
#define		PC_BEEP_Volume			0x0A00
#define		PHONE_Volume			0x0C00
#define		MIC_Volume				0x0E00
#define		LINE_IN_Volume			0x1000
#define		CD_Volume				0x1200
#define		VIDEO_Volume			0x1400
#define		AUX_Volume				0x1600
#define		PCM_OUT_Volume			0x1800
#define		RECORD_SELECT			0x1A00
#define		RECORD_GAIN				0x1C00
#define		RESERVED_REG_3			0x1E00
#define		GENERAL_PURPOSE			0x2000
#define		THREE_D_CONTROL_REG		0x2200
#define		RESERVED_REG_4			0x2400
#define		POWERDOWN_CTRL_STAT		0x2600
#define		SERIAL_CONFIGURATION	0x7400
#define		MISC_CONTROL_BITS		0x7600
#define		SAMPLE_RATE_GENERATE_0	0x7800
#define		SAMPLE_RATE_GENERATE_1	0x7A00
#define		VENDOR_ID_1				0x7C00
#define		VENDOR_ID_2				0x7E00

/* Mask bit selections in Serial Configuration Register for 
   accessing registers on any of the 3 codecs */
#define		MASTER_Reg_Mask			0x1000
#define		SLAVE1_Reg_Mask			0x2000
#define		SLAVE2_Reg_Mask			0x4000
#define		MASTER_SLAVE1			0x3000
#define		MASTER_SLAVE2			0x5000
#define		MASTER_SLAVE1_SLAVE2	0x7000

/* Macros for setting Bits 15, 14 and 13 in Slot 0 Tag Phase */
#define		ENABLE_VFbit_SLOT1_SLOT2	0xE000
#define		ENABLE_VFbit_SLOT1			0xC000



#define     AD1881_RESET_CYCLES 	80
			/* ad1881 RESET~ spec = 1.0(uS) min */
			/* 80(MIPs) = 12.5 (nS) cycle time, therefore >=    80 cycles */
#define     AD1881_WARMUP_CYCLES1    20000
#define		AD1881_WARMUP_CYCLES2    60000
			/* CYCLES1 + CYCLES2 = 80000 DSP instruction cycles total */
			/* ad1881 warm-up = 1.0(mS) */
			/* 80(MIPs) = 12.5 (nS) cycle time, therefore >= 80000 cycles */