maldcr.h

移植好的Ibm405ep bsp板极支持包

#define MAL_RCBS25   (0x69)   /* RX 25 Channel buffer size reg	 */
#define MAL_RCBS26   (0x6A)   /* RX 26 Channel buffer size reg	 */
#define MAL_RCBS27   (0x6B)   /* RX 27 Channel buffer size reg	 */
#define MAL_RCBS28   (0x6C)   /* RX 28 Channel buffer size reg	 */
#define MAL_RCBS29   (0x6D)   /* RX 29 Channel buffer size reg	 */
#define MAL_RCBS30   (0x6E)   /* RX 30 Channel buffer size reg	 */
#define MAL_RCBS31   (0x6F)   /* RX 31 Channel buffer size reg	 */

/*
 * MAL Configuration Register bits (MAL_CFG)
 */

#define MAL_CFG_SR	   0x80000000	   /* MAL software reset	      */
#define MAL_CFG_PLBP_MASK  0x00C00000	   /* PLB priority		      */
#define MAL_CFG_GA	   0x00200000	   /* Guarded active		      */
#define MAL_CFG_OA	   0x00100000	   /* Ordered active		      */
#define MAL_CFG_PLBLE	   0x00080000	   /* PLB Lock error		      */
#define MAL_CFG_PLBLT_MASK 0x00078000	   /* PLB latency timer 	      */
#define MAL_CFG_PLBB	   0x00004000	   /* PLB burst 		      */
#define MAL_CFG_OPBBL	   0x00000080	   /* OPB lock enable		      */
#define MAL_CFG_EOPIE	   0x00000004	   /* End of packet interrupt enable  */
#define MAL_CFG_LEA	   0x00000002	   /* Lock error active 	      */
#define MAL_CFG_SD	   0x00000001	   /* Scroll descriptor 	      */

/*
 * MAL Error Status Register bits (MAL_ESR)
 *    The 1st group of bits is for the "error status" part of the register
 *	 (locked or last occuring)
 *    The 2nd group of bits is for the "interrupt status" part of the register
 */

#define MAL_ESR_EVB	  0x80000000	   /* Is there a valid error?	      */
#define MAL_ESR_CID_RX	  0x40000000	   /* Is Channel ID an RX channel?    */
#define MAL_ESR_CID_MASK  0x3E000000	   /* Channel ID mask		      */
#define MAL_ESR_DE	  0x00100000	   /* TX descriptor (not first) error */
#define MAL_ESR_ONE	  0x00080000	   /* OPB non-fullword error	      */
#define MAL_ESR_OTE	  0x00040000	   /* OPB timeout error 	      */
#define MAL_ESR_OSE	  0x00020000	   /* OPB slave error		      */
#define MAL_ESR_PEIN	  0x00010000	   /* PLB error 		      */

#define MAL_ESR_DEI	  0x00000010	   /* TX descriptor (not first) error */
#define MAL_ESR_ONEI	  0x00000008	   /* OPB non-fullword error	      */
#define MAL_ESR_OTEI	  0x00000004	   /* OPB timeout error 	      */
#define MAL_ESR_OSEI	  0x00000002	   /* OPB slave error		      */
#define MAL_ESR_PBEI	  0x00000001	   /* PLB error 		      */

/*
 * MAL Interrupt Enable Register bits (MAL_IER)
 *   These bits enable the events that will cause the activation of
 *   EXT_IRQ_MAL_SERR in the Universal Interrupt Controller.
 */

#define MAL_IER_DE	  0x00000010	   /* TX descriptor (not first) error */
#define MAL_IER_NE	  0x00000008	   /* OPB non-fullword error	      */
#define MAL_IER_TE	  0x00000004	   /* OPB timeout error 	      */
#define MAL_IER_OPBE	  0x00000002	   /* OPB slave error		      */
#define MAL_IER_PLBE	  0x00000001	   /* PLB error 		      */

/*
 * More Register definitions for MAL lib
 */

/* MADMAL transmit and receive status/control bits  */
/* for COMMAC bits, refer to the COMMAC header file */

#define MAL_TX_CTRL_READY 0x8000
#define MAL_TX_CTRL_WRAP  0x4000
#define MAL_TX_CTRL_CM	  0x2000
#define MAL_TX_CTRL_LAST  0x1000
#define MAL_TX_CTRL_INTR  0x0400

#define MAL_RX_CTRL_EMPTY 0x8000
#define MAL_RX_CTRL_WRAP  0x4000
#define MAL_RX_CTRL_CM	  0x2000
#define MAL_RX_CTRL_LAST  0x1000
#define MAL_RX_CTRL_FIRST 0x0800
#define MAL_RX_CTRL_INTR  0x0400

      /* Configuration Reg  */
#define MAL_CR_MMSR	  0x80000000
#define MAL_CR_PLBP_0	  0x00000000   /* lowest	*/
#define MAL_CR_PLBP_1	  0x00400000 
#define MAL_CR_PLBP_2	  0x00800000
#define MAL_CR_PLBP_3	  0x00C00000   /* highest	*/
#define MAL_CR_PLBP_MASK  0x00C00000
#define MAL_CR_GA	  0x00200000
#define MAL_CR_OA	  0x00100000
#define MAL_CR_PLBLE	  0x00080000
#define MAL_CR_PLBLT_MASK 0x00078000
#define MAL_CR_PLBLT_1	  0x00040000
#define MAL_CR_PLBLT_2	  0x00020000
#define MAL_CR_PLBLT_3	  0x00010000
#define MAL_CR_PLBLT_4	  0x00008000
#define MAL_CR_PLBLT_DEFAULT 0x00078000 /* ????? */	  
#define MAL_CR_PLBB	  0x00004000
#define MAL_CR_OPBBL	  0x00000080
#define MAL_CR_EOPIE	  0x00000004
#define MAL_CR_LEA	  0x00000002
#define MAL_CR_MSD	  0x00000001

    /* Error Status Reg    */
#define MAL_ESR_EVB	  0x80000000
#define MAL_ESR_CID	  0x40000000
#define MAL_ESR_DE	  0x00100000
#define MAL_ESR_ONE	  0x00080000
#define MAL_ESR_OTE	  0x00040000
#define MAL_ESR_OSE	  0x00020000
#define MAL_ESR_PEIN	  0x00010000
      /* same bit position as the IER */
      /* VV			 VV   */
#define MAL_ESR_DEI	  0x00000010
#define MAL_ESR_ONEI	  0x00000008
#define MAL_ESR_OTEI	  0x00000004
#define MAL_ESR_OSEI	  0x00000002
#define MAL_ESR_PBEI	  0x00000001
      /* ^^			 ^^   */
      /* Mal IER		      */
#define MAL_IER_DE	  0x00000010
#define MAL_IER_NE	  0x00000008
#define MAL_IER_TE	  0x00000004
#define MAL_IER_OPBE	  0x00000002
#define MAL_IER_PLBE	  0x00000001

#define MAL_CHANNEL0	  0x80000000
#define MAL_CHANNEL1	  0x40000000
#define MAL_CHANNEL2	  0x20000000
#define MAL_CHANNEL3	  0x10000000
#define MAL_CHANNEL4	  0x08000000
#define MAL_CHANNEL5	  0x04000000
#define MAL_CHANNEL6	  0x02000000
#define MAL_CHANNEL7	  0x01000000
#define MAL_CHANNEL8	  0x00800000
#define MAL_CHANNEL9	  0x00400000
#define MAL_CHANNEL10	  0x00200000
#define MAL_CHANNEL11	  0x00100000
#define MAL_CHANNEL12	  0x00080000
#define MAL_CHANNEL13	  0x00040000
#define MAL_CHANNEL14	  0x00020000
#define MAL_CHANNEL15	  0x00010000
#define MAL_CHANNEL16	  0x00008000
#define MAL_CHANNEL17	  0x00004000
#define MAL_CHANNEL18	  0x00002000
#define MAL_CHANNEL19	  0x00001000
#define MAL_CHANNEL20	  0x00000800
#define MAL_CHANNEL21	  0x00000400
#define MAL_CHANNEL22	  0x00000200
#define MAL_CHANNEL23	  0x00000100
#define MAL_CHANNEL24	  0x00000080
#define MAL_CHANNEL25	  0x00000040
#define MAL_CHANNEL26	  0x00000020
#define MAL_CHANNEL27	  0x00000010
#define MAL_CHANNEL28	  0x00000008
#define MAL_CHANNEL29	  0x00000004
#define MAL_CHANNEL30	  0x00000002
#define MAL_CHANNEL31	  0x00000001

#define MAL_MAXDESCRIPTORS 256
#define MAL_MAXTXBLOCK	   4095
#define MAL_MAXRXBLOCK	   4080

#define MAL_BUFF_ALIGNMENT_MASK 0xFFFFFFE0  /* 32 byte buffer alignment */

#endif	/* INCmalDcrh */