maldcr.h

移植好的Ibm405ep bsp板极支持包

/* malDcr.h - IBM Memory Access Layer (MAL) DCR access assembly routines */

/*******************************************************************************
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   AS-IS basis.

   IT IS PROVIDED WITHOUT WARRANTY OF ANY KIND, INCLUDING THE WARRANTIES OF
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/* Copyright 2001 Wind River Systems, Inc. */

/*
modification history
--------------------
01b,07nov01,jtp  prepare for emac support
01a,24oct01,jtp  created from walnut malDcr.h version 01e
*/

/*
This file contains the definitions of the Device Control Register (DCR)
access functions of the IBM Memory Access Layer (MAL) core.
MAL is a hardware core in IBM's Blue Logic ASIC core library that is
normally situated between system memory and packet-oriented
Communications Media Access Controllers (COMMACS) in a chip. MAL's job
is to DMA data packets between the COMMACs and memory with minimal
processor core intervention.
*/

#ifndef INCmalDcrh
#define INCmalDcrh

/*
 * Memory Access Layer (MAL) core register OFFSETs. Each is a separate
 * DCR register.
 */

#define MAL_CFG      (0x00)   /* MAL Config reg 		 */
#define MAL_ESR      (0x01)   /* Error Status reg (Read/Clear)	 */
#define MAL_IER      (0x02)   /* Interrupt enable reg		 */
#define MAL_DBR      (0x03)   /* Mal Debug reg (Read only)	 */
#define MAL_TXCASR   (0x04)   /* TX Channel active reg (set)	 */
#define MAL_TXCARR   (0x05)   /* TX Channel active reg (Reset)	 */
#define MAL_TXEOBISR (0x06)   /* TX End of buffer int status reg */
#define MAL_TXDEIR   (0x07)   /* TX Descriptor Error Int reg	 */
#define MAL_RXCASR   (0x10)   /* RX Channel active reg (set)	 */
#define MAL_RXCARR   (0x11)   /* RX Channel active reg (Reset)	 */
#define MAL_RXEOBISR (0x12)   /* RX End of buffer int status reg */
#define MAL_RXDEIR   (0x13)   /* RX Descriptor Error Int reg	 */
#define MAL_TXCTPxR  (0x20)   /* TX 0 Channel table pointer reg  */
#define MAL_TXCTP0R  (0x20)   /* TX 0 Channel table pointer reg  */
#define MAL_TXCTP1R  (0x21)   /* TX 1 Channel table pointer reg  */
#define MAL_TXCTP2R  (0x22)   /* TX 2 Channel table pointer reg  */
#define MAL_TXCTP3R  (0x23)   /* TX 3 Channel table pointer reg  */
#define MAL_TXCTP4R  (0x24)   /* TX 4 Channel table pointer reg  */
#define MAL_TXCTP5R  (0x25)   /* TX 5 Channel table pointer reg  */
#define MAL_TXCTP6R  (0x26)   /* TX 6 Channel table pointer reg  */
#define MAL_TXCTP7R  (0x27)   /* TX 7 Channel table pointer reg  */
#define MAL_TXCTP8R  (0x28)   /* TX 8 Channel table pointer reg  */
#define MAL_TXCTP9R  (0x29)   /* TX 9 Channel table pointer reg  */
#define MAL_TXCTP10R (0x2A)   /* TX 10 Channel table pointer reg */
#define MAL_TXCTP11R (0x2B)   /* TX 11 Channel table pointer reg */
#define MAL_TXCTP12R (0x2C)   /* TX 12 Channel table pointer reg */
#define MAL_TXCTP13R (0x2D)   /* TX 13 Channel table pointer reg */
#define MAL_TXCTP14R (0x2E)   /* TX 14 Channel table pointer reg */
#define MAL_TXCTP15R (0x2F)   /* TX 15 Channel table pointer reg */
#define MAL_TXCTP16R (0x30)   /* TX 16 Channel table pointer reg */
#define MAL_TXCTP17R (0x31)   /* TX 17 Channel table pointer reg */
#define MAL_TXCTP18R (0x32)   /* TX 18 Channel table pointer reg */
#define MAL_TXCTP19R (0x33)   /* TX 19 Channel table pointer reg */
#define MAL_TXCTP20R (0x34)   /* TX 20 Channel table pointer reg */
#define MAL_TXCTP21R (0x35)   /* TX 21 Channel table pointer reg */
#define MAL_TXCTP22R (0x36)   /* TX 22 Channel table pointer reg */
#define MAL_TXCTP23R (0x37)   /* TX 23 Channel table pointer reg */
#define MAL_TXCTP24R (0x38)   /* TX 24 Channel table pointer reg */
#define MAL_TXCTP25R (0x39)   /* TX 25 Channel table pointer reg */
#define MAL_TXCTP26R (0x3A)   /* TX 26 Channel table pointer reg */
#define MAL_TXCTP27R (0x3B)   /* TX 27 Channel table pointer reg */
#define MAL_TXCTP28R (0x3C)   /* TX 28 Channel table pointer reg */
#define MAL_TXCTP29R (0x3D)   /* TX 29 Channel table pointer reg */
#define MAL_TXCTP30R (0x3E)   /* TX 30 Channel table pointer reg */
#define MAL_TXCTP31R (0x3F)   /* TX 31 Channel table pointer reg */

#define MAL_RXCTPxR  (0x40)   /* RX 0 Channel table pointer reg  */
#define MAL_RXCTP0R  (0x40)   /* RX 0 Channel table pointer reg  */
#define MAL_RXCTP1R  (0x41)   /* RX 1 Channel table pointer reg  */
#define MAL_RXCTP2R  (0x42)   /* RX 2 Channel table pointer reg  */
#define MAL_RXCTP3R  (0x43)   /* RX 3 Channel table pointer reg  */
#define MAL_RXCTP4R  (0x44)   /* RX 4 Channel table pointer reg  */
#define MAL_RXCTP5R  (0x45)   /* RX 5 Channel table pointer reg  */
#define MAL_RXCTP6R  (0x46)   /* RX 6 Channel table pointer reg  */
#define MAL_RXCTP7R  (0x47)   /* RX 7 Channel table pointer reg  */
#define MAL_RXCTP8R  (0x48)   /* RX 8 Channel table pointer reg  */
#define MAL_RXCTP9R  (0x49)   /* RX 9 Channel table pointer reg  */
#define MAL_RXCTP10R (0x4A)   /* RX 10 Channel table pointer reg */
#define MAL_RXCTP11R (0x4B)   /* RX 11 Channel table pointer reg */
#define MAL_RXCTP12R (0x4C)   /* RX 12 Channel table pointer reg */
#define MAL_RXCTP13R (0x4D)   /* RX 13 Channel table pointer reg */
#define MAL_RXCTP14R (0x4E)   /* RX 14 Channel table pointer reg */
#define MAL_RXCTP15R (0x4F)   /* RX 15 Channel table pointer reg */
#define MAL_RXCTP16R (0x50)   /* RX 16 Channel table pointer reg */
#define MAL_RXCTP17R (0x51)   /* RX 17 Channel table pointer reg */
#define MAL_RXCTP18R (0x52)   /* RX 18 Channel table pointer reg */
#define MAL_RXCTP19R (0x53)   /* RX 19 Channel table pointer reg */
#define MAL_RXCTP20R (0x54)   /* RX 20 Channel table pointer reg */
#define MAL_RXCTP21R (0x55)   /* RX 21 Channel table pointer reg */
#define MAL_RXCTP22R (0x56)   /* RX 22 Channel table pointer reg */
#define MAL_RXCTP23R (0x57)   /* RX 23 Channel table pointer reg */
#define MAL_RXCTP24R (0x58)   /* RX 24 Channel table pointer reg */
#define MAL_RXCTP25R (0x59)   /* RX 25 Channel table pointer reg */
#define MAL_RXCTP26R (0x5A)   /* RX 26 Channel table pointer reg */
#define MAL_RXCTP27R (0x5B)   /* RX 27 Channel table pointer reg */
#define MAL_RXCTP28R (0x5C)   /* RX 28 Channel table pointer reg */
#define MAL_RXCTP29R (0x5D)   /* RX 29 Channel table pointer reg */
#define MAL_RXCTP30R (0x5E)   /* RX 30 Channel table pointer reg */
#define MAL_RXCTP31R (0x5F)   /* RX 31 Channel table pointer reg */

#define MAL_RCBSx    (0x60)   /* RX 0 Channel buffer size reg	 */
#define MAL_RCBS0    (0x60)   /* RX 0 Channel buffer size reg	 */
#define MAL_RCBS1    (0x61)   /* RX 1 Channel buffer size reg	 */
#define MAL_RCBS2    (0x62)   /* RX 2 Channel buffer size reg	 */
#define MAL_RCBS3    (0x63)   /* RX 3 Channel buffer size reg	 */
#define MAL_RCBS4    (0x64)   /* RX 4 Channel buffer size reg	 */
#define MAL_RCBS5    (0x65)   /* RX 5 Channel buffer size reg	 */
#define MAL_RCBS6    (0x66)   /* RX 6 Channel buffer size reg	 */
#define MAL_RCBS7    (0x67)   /* RX 7 Channel buffer size reg	 */
#define MAL_RCBS8    (0x68)   /* RX 8 Channel buffer size reg	 */
#define MAL_RCBS9    (0x69)   /* RX 9 Channel buffer size reg	 */
#define MAL_RCBS10   (0x6A)   /* RX 10 Channel buffer size reg	 */
#define MAL_RCBS11   (0x6B)   /* RX 11 Channel buffer size reg	 */
#define MAL_RCBS12   (0x6C)   /* RX 12 Channel buffer size reg	 */
#define MAL_RCBS13   (0x6D)   /* RX 13 Channel buffer size reg	 */
#define MAL_RCBS14   (0x6E)   /* RX 14 Channel buffer size reg	 */
#define MAL_RCBS15   (0x6F)   /* RX 15 Channel buffer size reg	 */
#define MAL_RCBS16   (0x60)   /* RX 16 Channel buffer size reg	 */
#define MAL_RCBS17   (0x61)   /* RX 17 Channel buffer size reg	 */
#define MAL_RCBS18   (0x62)   /* RX 18 Channel buffer size reg	 */
#define MAL_RCBS19   (0x63)   /* RX 19 Channel buffer size reg	 */
#define MAL_RCBS20   (0x64)   /* RX 20 Channel buffer size reg	 */
#define MAL_RCBS21   (0x65)   /* RX 21 Channel buffer size reg	 */
#define MAL_RCBS22   (0x66)   /* RX 22 Channel buffer size reg	 */
#define MAL_RCBS23   (0x67)   /* RX 23 Channel buffer size reg	 */
#define MAL_RCBS24   (0x68)   /* RX 24 Channel buffer size reg	 */