uicdcr.h

移植好的Ibm405ep bsp板极支持包

/* uicDcr.h - IBM Universal Int Controller (UIC) DCR access assembly routines */

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/* Copyright 1984-1999 Wind River Systems, Inc. */

/*
modification history
--------------------
01c,11jul02,mcg  removed function prototypes now that sysDcr.s exists
01b,15may00,mcg  register name updates to match 405GP User Manual
01a,21sep99,mcg  created
*/

/*
This file contains the definitions of the UIC interrupt controller DCR register
access functions.
*/

#ifndef INCuicDcrh
#define INCuicDcrh

/*
 * Universal Interrupt Controller register definitions. Each is a separate
 * DCR register.
 */

#define UIC0_SR        (UIC0_DCR_BASE+0x0)  /* UIC status                     */
#define UIC0_ER        (UIC0_DCR_BASE+0x2)  /* UIC enable                     */
#define UIC0_CR        (UIC0_DCR_BASE+0x3)  /* UIC critical                   */
#define UIC0_PR        (UIC0_DCR_BASE+0x4)  /* UIC polarity                   */
#define UIC0_TR        (UIC0_DCR_BASE+0x5)  /* UIC triggering                 */
#define UIC0_MSR       (UIC0_DCR_BASE+0x6)  /* UIC masked status              */
#define UIC0_VR        (UIC0_DCR_BASE+0x7)  /* UIC vector                     */
#define UIC0_VCR       (UIC0_DCR_BASE+0x8)  /* UIC vector configuration       */

#endif  /* INCuicDcrh */