ppc405ep.h

移植好的Ibm405ep bsp板极支持包

/* ppc405EP.h - IBM PowerPC 405EP Chip header */

/*******************************************************************************
   This source and object code has been made available to you by IBM on an
   AS-IS basis.

   IT IS PROVIDED WITHOUT WARRANTY OF ANY KIND, INCLUDING THE WARRANTIES OF
   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE OR OF NONINFRINGEMENT
   OF THIRD PARTY RIGHTS.  IN NO EVENT SHALL IBM OR ITS LICENSORS BE LIABLE
   FOR INCIDENTAL, CONSEQUENTIAL OR PUNITIVE DAMAGES.  IBM芐 OR ITS LICENSOR芐
   DAMAGES FOR ANY CAUSE OF ACTION, WHETHER IN CONTRACT OR IN TORT, AT LAW OR
   AT EQUITY, SHALL BE LIMITED TO A MAXIMUM OF $1,000 PER LICENSE.  No license
   under IBM patents or patent applications is to be implied by the copyright
   license.

   Any user of this software should understand that neither IBM nor its
   licensors will be responsible for any consequences resulting from the use
   of this software.

   Any person who transfers this source code or any derivative work must
   include the IBM copyright notice, this paragraph, and the preceding two
   paragraphs in the transferred software.

   Any person who transfers this object code or any derivative work must
   include the IBM copyright notice in the transferred software.

   COPYRIGHT   I B M   CORPORATION 2000
   LICENSED MATERIAL  -  PROGRAM PROPERTY OF  I B M"

*******************************************************************************/

/* Copyright 1984-1999 Wind River Systems, Inc. */

/*
modification history
--------------------
01b,06sep02,mcg  added 405EP rev 1.1 EMAC noise filters and JTAG ID definitions
01a,20may02,mcg  created from ppc405GP.h rev 01f
*/

/*
This file contains DCR (Device Control Register) addresses and other chip
specific information for the IBM PowerPC 405EP outside of the 405 processor
core (see ppc405.h for 405 processor core information).
*/

#ifndef INCppc405EPh
#define INCppc405EPh


/*
 * The 405EP chip uses the 405D4 processor core which has a 16KB I-cache and a
 * 16KB D-cache.  All 405 processor cores have 32 byte cache lines, and are
 * 2-way set associative.
 */

#define _ICACHE_LINE_NUM_405EP  256                    /* 256 * 32 * 2 = 16KB */
#define _DCACHE_LINE_NUM_405EP  256                    /* 256 * 32 * 2 = 16KB */


/*
 * Processor Version Register (PVR) values for 405EP
 * CPC0_JTAGID values for 405EP.
 */

#define PVR_405EP       0x51210950       /* 405EP Revision A and B            */

#define JTAGID_405EP_REVA  0x10267049    /* JTAG ID register value for Rev A  */
#define JTAGID_405EP_REVB  0x20267049    /* JTAG ID register value for Rev B  */


/*
 * Reduce the number of MAL channel DCR access functions because a MAL with
 * only 8 channels is used in the 405EP.
 */

#define MAL_CHANNELS_8

/*
 * Valid Memory Access Layer (MAL) channels.  On the 405EP, the two EMACs are
 * the only communications cores that uses MAL.  Each has 2 TX channels, and 1
 * RX channel.
 */

#define MAL_CHN_TX_405EP  0xF0000000      /* TX channels 0,1,2 and 3          */
#define MAL_CHN_RX_405EP  0xC0000000      /* RX channel  0 and 1              */

/*
 * MAL channels numbers the EMAC Ethernet controller is connected to on 405EP.
 * This information is put into the EMAC driver END load string.
 */

#define EMAC0_TX_CHN_0_405EP     0
#define EMAC0_TX_CHN_1_405EP     1
#define EMAC1_TX_CHN_0_405EP     2
#define EMAC1_TX_CHN_1_405EP     3

#define EMAC0_RX_CHN_0_405EP     0
#define EMAC1_RX_CHN_0_405EP     1

/*
 * Base DCR address values for all perhipheral cores in the 405EP
 */

#define SDRAM0_DCR_BASE       0x010       /* SDRAM Controller                 */
#define EBC0_DCR_BASE         0x012       /* External Bus Controller          */
#define UIC0_DCR_BASE         0x0C0       /* Universal Interrupt Controller   */
#define DMA0_DCR_BASE         0x100       /* DMA Controller                   */
#define MISC_DCR_BASE         0x0F0       /* Miscellaneous DCRs               */
#define MAL0_DCR_BASE         0x180       /* Memory Access Layer Core         */
#define DCP0_DCR_BASE         0x014       /* Code Decompression Core          */
#define OCM0_DCR_BASE         0x018       /* On-chip Memory Controller        */
#define CPM_DCR_BASE          0x0B8       /* Power Management                 */

/*
 * Static interrupt vectors/levels.  These also correspond to bit numbers in
 * many of the registers of the Universal Interrupt Controller.
 */
#define INT_VEC_UART0             0
#define INT_VEC_UART1             1
#define INT_VEC_IIC               2
#define INT_VEC_PCI               3
#define INT_VEC_DMA_CH0           5
#define INT_VEC_DMA_CH1           6
#define INT_VEC_DMA_CH2           7
#define INT_VEC_DMA_CH3           8
#define INT_VEC_ENET_WAKEUP       9
#define INT_VEC_MAL_SERR          10
#define INT_VEC_MAL_TXEOB         11
#define INT_VEC_MAL_RXEOB         12
#define INT_VEC_MAL_TXDE          13
#define INT_VEC_MAL_RXDE          14
#define INT_VEC_ETHERNET_0        15
#define INT_VEC_PCI_SERR          16
#define INT_VEC_ETHERNET_1        17
#define INT_VEC_PCI_PWR           18
#define INT_VEC_GPT0              19
#define INT_VEC_GPT1              20
#define INT_VEC_GPT2              21
#define INT_VEC_GPT3              22
#define INT_VEC_GPT4              23
#define INT_VEC_EXT_IRQ_0         25
#define INT_VEC_EXT_IRQ_1         26
#define INT_VEC_EXT_IRQ_2         27
#define INT_VEC_EXT_IRQ_3         28
#define INT_VEC_EXT_IRQ_4         29
#define INT_VEC_EXT_IRQ_5         30
#define INT_VEC_EXT_IRQ_6         31


#define INT_LVL_UART0             0
#define INT_LVL_UART1             1
#define INT_LVL_IIC               2
#define INT_LVL_PCI               3
#define INT_LVL_DMA_CH0           5
#define INT_LVL_DMA_CH1           6
#define INT_LVL_DMA_CH2           7
#define INT_LVL_DMA_CH3           8
#define INT_LVL_ENET_WAKEUP       9
#define INT_LVL_MAL_SERR          10
#define INT_LVL_MAL_TXEOB         11
#define INT_LVL_MAL_RXEOB         12
#define INT_LVL_MAL_TXDE          13
#define INT_LVL_MAL_RXDE          14
#define INT_LVL_ETHERNET_0        15
#define INT_LVL_PCI_SERR          16
#define INT_LVL_ETHERNET_1        17
#define INT_LVL_PCI_PWR           18
#define INT_LVL_GPT0              19
#define INT_LVL_GPT1              20
#define INT_LVL_GPT2              21
#define INT_LVL_GPT3              22
#define INT_LVL_GPT4              23
#define INT_LVL_EXT_IRQ_0         25
#define INT_LVL_EXT_IRQ_1         26
#define INT_LVL_EXT_IRQ_2         27
#define INT_LVL_EXT_IRQ_3         28
#define INT_LVL_EXT_IRQ_4         29
#define INT_LVL_EXT_IRQ_5         30
#define INT_LVL_EXT_IRQ_6         31

/*
 * Clock, power management, chip control and strapping register defintions.
 * Each is a separate DCR register.
 */
#define CPC0_PLLMR0 (MISC_DCR_BASE+0x0)      /* sysClockControl               */
#define CPC0_BOOT   (MISC_DCR_BASE+0x1)      /* clockStatus                   */
#define CPC0_CR1    (MISC_DCR_BASE+0x2)      /* cpuDCR                        */
#define CPC0_EPRCSR (MISC_DCR_BASE+0x3)      /* enetDCR                       */
#define CPC0_PLLMR1 (MISC_DCR_BASE+0x4)      /* sysPLLControl                 */
#define CPC0_UCR    (MISC_DCR_BASE+0x5)      /* uartDCR                       */
#define CPC0_SRR    (MISC_DCR_BASE+0x6)      /* Soft Reset Register           */
#define CPC0_JTAGID (MISC_DCR_BASE+0x7)      /* JTAG ID                       */
#define CPC0_PCI    (MISC_DCR_BASE+0x9)      /* pciDCR                        */

#define CPC0_ER     (CPM_DCR_BASE+0x0)       /* PMR0 Power Management Enable  */
#define CPC0_FR     (CPM_DCR_BASE+0x1)       /* PMFR Power Management Force   */
#define CPC0_SR     (CPM_DCR_BASE+0x2)       /* PMSR Power Management Status  */

/* Bit definitions */
#define PLLMR0_CPU_DIV_MASK      0x00300000     /* CPU clock divider */
#define PLLMR0_CPU_DIV_BIT_SHIFT     20
#define PLLMR0_CPU_DIV_1         0x00000000
#define PLLMR0_CPU_DIV_2         0x00100000
#define PLLMR0_CPU_DIV_3         0x00200000
#define PLLMR0_CPU_DIV_4         0x00300000

#define PLLMR0_PLB_DIV_MASK      0x00030000     /* PLB clock divider */
#define PLLMR0_PLB_DIV_BIT_SHIFT     16
#define PLLMR0_PLB_DIV_1         0x00000000
#define PLLMR0_PLB_DIV_2         0x00010000
#define PLLMR0_PLB_DIV_3         0x00020000
#define PLLMR0_PLB_DIV_4         0x00030000

#define PLLMR0_OPB_DIV_MASK      0x00003000     /* OPB clock divider */
#define PLLMR0_OPB_DIV_BIT_SHIFT     12
#define PLLMR0_OPB_DIV_1         0x00000000
#define PLLMR0_OPB_DIV_2         0x00001000
#define PLLMR0_OPB_DIV_3         0x00002000
#define PLLMR0_OPB_DIV_4         0x00003000

#define PLLMR0_EBC_DIV_MASK      0x00000300     /* EBC clock divider */
#define PLLMR0_EBC_DIV_BIT_SHIFT      8
#define PLLMR0_EBC_DIV_2         0x00000000
#define PLLMR0_EBC_DIV_3         0x00000100
#define PLLMR0_EBC_DIV_4         0x00000200
#define PLLMR0_EBC_DIV_5         0x00000300

#define PLLMR0_MAL_DIV_MASK      0x00000030     /* MAL clock divider */
#define PLLMR0_MAL_DIV_BIT_SHIFT      4
#define PLLMR0_MAL_DIV_1         0x00000000
#define PLLMR0_MAL_DIV_2         0x00000010
#define PLLMR0_MAL_DIV_3         0x00000020
#define PLLMR0_MAL_DIV_4         0x00000030

#define PLLMR0_PCI_DIV_MASK      0x00000003     /* PCI clock divider */
#define PLLMR0_PCI_DIV_BIT_SHIFT      0
#define PLLMR0_PCI_DIV_1         0x00000000
#define PLLMR0_PCI_DIV_2         0x00000001
#define PLLMR0_PCI_DIV_3         0x00000002
#define PLLMR0_PCI_DIV_4         0x00000003

#define BOOT_SEEPROM_ADRS        0x00000060     /* SEEPROM adrs lower 2 bits */
#define BOOT_EBC_PCI             0x00000010     /*                           */
#define BOOT_EBC_WIDTH           0x0000000C     /* Width of boot device      */
#define BOOT_SEEPROM_PRES        0x00000002     /* SEEPROM used at boot      */
#define BOOT_PLL_LOCK            0x00000001     /* SYSPLL lock               */

#define CPU_EXT_TIMER_EN         0x00000004     /* External timer clock      */
#define CPU_OP_FWD_EN            0x00000002     /* Operand forwarding        */
#define CPU_DET_MULT_EN          0x00000001     /* Deterministic multiply    */

#define EPRCSR_NOISE_FILTER_0    0x80000000     /* Noise Filter for EMAC0    */
#define EPRCSR_NOISE_FILTER_1    0x40000000     /* Noise Filter for EMAC1    */
#define EPRCSR_NOISE_FILTER_BOTH 0xC0000000     /* Noise Filter for both     */
#define EPRCSR_REJ_PKT_POL_1     0x00000080     /* Polarity of Reject signal */
#define EPRCSR_REJ_PKT_POL_0     0x00000040     /* Polarity of Reject signal */
#define EPRCSR_REMOVE_EN_1       0x00000020     /* Remove packet enable      */
#define EPRCSR_REMOVE_EN_0       0x00000010     /* Remove packet enable      */
#define EPRCSR_RX_TX_CLK_1       0x00000002     /* RX clock for loopback     */
#define EPRCSR_RX_TX_CLK_0       0x00000001     /* RX clock for loopback     */

#define PLLMR1_PLL_ENGAGE        0x80000000
#define PLLMR1_PLL_RESET         0x40000000

#define PLLMR1_FB_DIV_MASK       0x00F00000     /* Feedback multiplier       */
#define PLLMR1_FB_DIV_BIT_SHIFT      20
#define PLLMR1_FB_DIV_16         0x00000000
#define PLLMR1_FB_DIV_1          0x00100000
#define PLLMR1_FB_DIV_2          0x00200000
#define PLLMR1_FB_DIV_3          0x00300000
#define PLLMR1_FB_DIV_4          0x00400000
#define PLLMR1_FB_DIV_5          0x00500000
#define PLLMR1_FB_DIV_6          0x00600000
#define PLLMR1_FB_DIV_7          0x00700000
#define PLLMR1_FB_DIV_8          0x00800000
#define PLLMR1_FB_DIV_9          0x00900000
#define PLLMR1_FB_DIV_10         0x00A00000
#define PLLMR1_FB_DIV_11         0x00B00000
#define PLLMR1_FB_DIV_12         0x00C00000
#define PLLMR1_FB_DIV_13         0x00D00000
#define PLLMR1_FB_DIV_14         0x00E00000
#define PLLMR1_FB_DIV_15         0x00F00000

#define PLLMR1_FWDA_DIV_MASK     0x00070000     /* Forward A divider */
#define PLLMR1_FWDA_DIV_BIT_SHIFT    16
#define PLLMR1_FWDA_DIV_8        0x00000000
#define PLLMR1_FWDA_DIV_7        0x00010000
#define PLLMR1_FWDA_DIV_6        0x00020000
#define PLLMR1_FWDA_DIV_5        0x00030000
#define PLLMR1_FWDA_DIV_4        0x00040000
#define PLLMR1_FWDA_DIV_3        0x00050000
#define PLLMR1_FWDA_DIV_2        0x00060000
#define PLLMR1_FWDA_DIV_1        0x00070000

#define PLLMR1_FWDB_DIV_MASK     0x00007000     /* Forward B divider */
#define PLLMR1_FWDB_DIV_BIT_SHIFT    12
#define PLLMR1_FWDB_DIV_8        0x00000000
#define PLLMR1_FWDB_DIV_7        0x00001000
#define PLLMR1_FWDB_DIV_6        0x00002000
#define PLLMR1_FWDB_DIV_5        0x00003000
#define PLLMR1_FWDB_DIV_4        0x00004000
#define PLLMR1_FWDB_DIV_3        0x00005000
#define PLLMR1_FWDB_DIV_2        0x00006000
#define PLLMR1_FWDB_DIV_1        0x00007000

#define PLLMR1_TUNE_MASK         0x000003FF
#define PLLMR1_TUNE_2_M_3        0x00000133     /*  2 <= M <= 3               */
#define PLLMR1_TUNE_4_M_6        0x00000134     /*  3 <  M <= 6               */
#define PLLMR1_TUNE_7_M_10       0x00000138     /*  6 <  M <= 10              */
#define PLLMR1_TUNE_11_M_14      0x0000013C     /* 10 <  M <= 14              */
#define PLLMR1_TUNE_15_M_40      0x0000023E     /* 14 <  M <= 40              */
#define PLLMR1_TUNE_VCO_LOW      0x00000000     /* 500MHz <= VCO <=  800MHz   */
#define PLLMR1_TUNE_VCO_HI       0x00000080     /* 800MHz <  VCO <= 1000MHz   */

#define UCR_UART_DMA_CL_0        0x00200000     /* UART0 DMA                  */
#define UCR_UART_DMA_TX_0        0x00100000
#define UCR_UART_DMA_RX_0        0x00080000
#define UCR_UART_DMA_CL_1        0x00040000     /* UART1 DMA                  */
#define UCR_UART_DMA_TX_1        0x00020000