vx_rw_flash.cmd

移植好的Ibm405ep bsp板极支持包

###############################################################################
#
# IBM RISCWatch command file for updating the ibmEvb405EP board flash with a
# VxWorks bootrom image (bootrom.hex or bootrom_uncmp.hex).  JTAG RISCWatch is
# required.
#
#
# Usage:  From a RISCWatch command line type one the following commands:
#
#            exec vx_rw_flash.cmd {"bootrom_uncmp.hex"}
#
#            exec vx_rw_flash.cmd {"bootrom_.hex"}
#
#
# This utility makes the following assumptions:
#      - An AMD Am29F040 (512KB) flash part is being used.
#      - ROM_TEXT_ADRS in Makefile and config.h equals 0xfff80100.
#
# modification history
# --------------------
# 01c,28may02,mcg  update for ibmEvb405EP
# 01b,10jul00,mcg  fixed polling, changed from chip to system reset
# 01a,27apr00,mcg  created
#
#

#
# Reset the chip
#
parms {input_file}                  # filename parameter being passed in
unload all
window output
print "Initializing 405EP."

create temp
create mode		      # for SDRAM addressing mode
create data
create read_dev_addr 	      # for IIC read device address
create write_dev_addr         # for IIC write device address

# Give RISCWatch access to internal MMIO
memacc add 0xef600500 0xef60051f    # IIC

# This will reset the board and leave the CPU bypassed (16.6 MHz)
jtag clock 5     # slow down RISCWatch TCLK until PLL is set
halt on
reset sys
stop
halt off
stop

#
# Initialize EBC Bank 0 for FLASH
#
write EBC0_B0AP    0x04006000
write EBC0_B0CR    0xFFF18000

#----------------------------------------------------------------------
# PLL Initialization
# Set to :
#   CPU = 200MHz
#   PLB = CPU/2 = 100 MHz
#   EBC = PLB/2 =  50 MHz
#   OPB = PLB/2 =  50 MHz
#----------------------------------------------------------------------
write CPC0_PLLMR0 0x00111002
write CPC0_PLLMR1 0x80C6623E
DELAY 2
jtag clock 10M

#----------------------------------------------------------------------
# Set the DIMM's EEPROM IIC device addresses
#----------------------------------------------------------------------
set read_dev_addr = 0xAB
set write_dev_addr = 0xAA

#----------------------------------------------------------------------
# We will read the EEPROM on the DIMM to determine the addressing
# mode required for programming the SDRAM memory
# controller. We determine the mode by reading byte 3 (# rows),
# byte 4 (# cols), and byte 17 (# internal banks) from the DIMM's
# EEPROM.
#----------------------------------------------------------------------
# Initialize the IIC contoller
#----------------------------------------------------------------------
write IIC0_LMADR    0x0              # clear lo master addr
write IIC0_HMADR    0x0              # clear hi master addr
write IIC0_LSADR    0x0              # clear lo slave addr
write IIC0_HSADR    0x0              # clear hi slave addr
write IIC0_STS      0x08             # clear status
write IIC0_EXTSTS   0x8F             # clear extended status
write IIC0_CLKDIV   0x03             # set clock div
write IIC0_INTRMSK  0x0              # no interrupts
write IIC0_XFRCNT   0x0              # clear transfer count
write IIC0_XTCNTLSS 0xF0             # clear extended control & status
write IIC0_MDCNTL   0x43             # set mode control (flush master
                                     #  data buf, enable hold SCL,
                                     #  exit unknown state)
write IIC0_CNTL     0x0              # clear control reg

#----------------------------------------------------------------------
# IIC Write - we must write the DIMM's EEPROM with the value of the byte
# to be read before it can be read.
#----------------------------------------------------------------------
write IIC0_STS 0x08               # clear status
read IIC0_STS data                # read status

while ((data & 0x01) == 0x01)     # ensure no transfers pending
  read IIC0_STS data
endwhile

read IIC0_MDCNTL data             # read mode control
set data = data|0x40              # set flush master data buf bit
write IIC0_MDCNTL data            # set mode control
write IIC0_LMADR write_dev_addr   # set lo master adr to dev adr
write IIC0_MDBUF 3                # set master data buf to dev sub adr
                                  # (starting byte to read) - here we set
			          # it to 3 to start the read from byte 3
write IIC0_CNTL 0x01              # set control to do a one byte write
read IIC0_STS data                # check status

while ((data & 0x01) == 0x01)      # wait till transfer complete
  read IIC0_STS data
endwhile

#----------------------------------------------------------------------
# IIC Read - read bytes 3 (# rows) and 4 i(# cols) from the DIMM's
# EEPROM.
#----------------------------------------------------------------------
write IIC0_STS 0x08               # clear status
read IIC0_STS data                # read status

while ((data & 0x01) == 0x01)     # ensure no transfers pending
  read IIC0_STS data
endwhile

read IIC0_MDCNTL data             # read mode control
set data = data|0x40              # set flush master data buf bit
write IIC0_MDCNTL data            # set mode control
write IIC0_LMADR read_dev_addr    # set lo master adr to dev adr
write IIC0_CNTL 0x13              # set control to do a two byte read
read IIC0_STS data                # check status

while ((data & 0x01) == 0x01)     # wait till transfer complete
  read IIC0_STS data
endwhile

set temp = 0x0
read IIC0_MDBUF data              # read master buf to get the byte 3(# rows)
set temp = data
read IIC0_MDBUF data              # read master buf to get the byte 4(# cols)
set temp = (temp<<8) | data

#----------------------------------------------------------------------
# IIC Write - must write the DIMM EEPROM with the value of the byte
# to be read before it can be read.
#----------------------------------------------------------------------
write IIC0_STS 0x08               # clear status
read IIC0_STS data                # read status

while ((data & 0x01) == 0x01)     # ensure no transfers pending
  read IIC0_STS data
endwhile

read IIC0_MDCNTL data             # read mode control
set data = data|0x40              # set flush master data buf bit
write IIC0_MDCNTL data            # set mode control
write IIC0_LMADR write_dev_addr   # set lo master adr to dev adr
write IIC0_MDBUF 17               # set master data buf to dev sub adr
                                  # (starting byte to read) - here we want to
                                  # read byte 17 for # internal banks
write IIC0_CNTL 0x01              # set control to do a one byte write
read IIC0_STS data                # check status

while ((data & 0x01) == 0x01)     # wait till transfer complete
  read IIC0_STS data
endwhile

#----------------------------------------------------------------------
# IIC Read - read byte 17 (# internal banks) from the DIMM's
# EEPROM.
#----------------------------------------------------------------------
write IIC0_STS 0x08               # clear status
read IIC0_STS data                # read status

while ((data & 0x01) == 0x01)     # ensure no transfers pending
  read IIC0_STS data
endwhile

read IIC0_MDCNTL data             # read mode control
set data = data|0x40              # set flush master data buf bit
write IIC0_MDCNTL data            # set mode control
write IIC0_LMADR read_dev_addr    # set lo master adr to dev adr
write IIC0_CNTL 0x03              # set control to do a one byte read
read IIC0_STS data                # check status

while ((data & 0x01) == 0x01)     # wait till transfer complete