syslib.c.bak

移植好的Ibm405ep bsp板极支持包

*
* sysProcNumSet - set the processor number
*
* This routine sets the processor number for the CPU board.
* Processor numbers should be unique on a single backplane.
*
* NOTE: This routine has no effect, since there is no VMEbus.
* RETURNS: N/A
*
* SEE ALSO: sysProcNumGet(),
*/

void sysProcNumSet
    (
    int procNum /* processor number (ignored in this BSP) */
    )
    {
    sysProcNum = sysProcNumGet();
    }

/*******************************************************************************
*
* sysIntLockLevelSet - set the current interrupt lock-out level
*
* This routine sets the current interrupt lock-out level.
*
* NOTE: This routine has no effect, since the facility is currently not
* implemented.
*
* RETURNS: ERROR, always.
*/

int sysIntLockLevelSet
    (
    int newLvl    /* new interrupt level */
    )
    {
    return (ERROR);
    }

/*******************************************************************************
*
* sysLocalDelay - delay of <ms_delay> milliseconds used before kernel is up
*
*
* RETURNS: N/A.
*/
void sysLocalDelay
    (
    UINT32 ms_delay
    )
    {
    UINT32 start_upper;
    UINT32 start_lower;
    UINT32 end_upper;
    UINT32 end_lower;
    UINT32 upper;
    UINT32 lower;
    UINT32 delay;
    BOOL timesup = FALSE;

    /*
     *  Read the timebase twice to start
     */
    vxTimeBaseGet (&start_upper, &start_lower);
    vxTimeBaseGet (&end_upper, &end_lower);

    while (timesup == FALSE)
        {

        /*
         * Determine if the delay has been long enough
         */
        upper = end_upper - start_upper;
        if (start_lower > end_lower)
            upper--;
        lower = end_lower - start_lower;

        delay =  1000 * upper * (0xFFFFFFFF / sysTimerClkFreq);
        delay += lower / (sysTimerClkFreq / 1000);

        if (delay > ms_delay)
            {
            timesup = TRUE;
            }
            else
            {
            vxTimeBaseGet (&end_upper, &end_lower);
            }
        }
    return;
    }


/*******************************************************************************
*
* sysInfoGet - determines system information (clock frequencies, etc.) based on
*              board switch and jumper settings.
*
* This routine returns information about the current operating environment of
* the board.  Optionally, it prints the information out.
*
* RETURNS: OK or ERROR.
*/

STATUS sysInfoGet
    (
    SYS_INFO    * sysInfo,
    int           verbose
    )
    {

   /* UCHAR   fpgaReg1;*/
    UCHAR   c9531Mult;
    UINT32  pllmr0;
    UINT32  pllmr1;
    UINT32  sysClkPeriodNs;
    UINT32  multM=1;


    bzero((char *)sysInfo, sizeof(SYS_INFO));


   /* fpgaReg1 = sysInByte(FPGA_REG1);  add by lp ,2004.10.18*/

    /*
     * Determine the clock frequency supplied to the 405EP by the
     * Cypress c9531.  The C9531 has an input clock of 33.3 MHz and
     * multiplies it by 1,2,3 or 4 depending on the setting of two
     * jumpers on the board.
     */
         /***************change by liping ,2004.9.15**********************/
   /* c9531Mult = 1 + ((fpgaReg1 & FPGA_REG1_CLOCK_MASK)
                          >> FPGA_REG1_CLOCK_BIT_SHIFT);*/
    
    c9531Mult=1;                      
    sysInfo->freqInput = C9531_INPUT_FREQ * c9531Mult;

    /* Calculate the period of the input clock in nanoseconds */

    sysClkPeriodNs = ONE_BILLION / sysInfo->freqInput;

    /*
     * Read 405EP PLL Mode registers
     */
    pllmr0 = sysDcrInLong(CPC0_PLLMR0);
    pllmr1 = sysDcrInLong(CPC0_PLLMR1);

    if (verbose)
        printf("\n");

    /*
     * Determine FWDA_DIV.
     */

    sysInfo->pllFwdADiv = 8 - ((pllmr1 & PLLMR1_FWDA_DIV_MASK) >> PLLMR1_FWDA_DIV_BIT_SHIFT);

    /*
     * Determine FWDB_DIV.
     */

    sysInfo->pllFwdBDiv = 8 - ((pllmr1 & PLLMR1_FWDB_DIV_MASK) >> PLLMR1_FWDB_DIV_BIT_SHIFT);

    /*
     * Determine FBK_DIV.
     */

    sysInfo->pllFbkDiv = (pllmr1 & PLLMR1_FB_DIV_MASK) >> PLLMR1_FB_DIV_BIT_SHIFT;
    if (sysInfo->pllFbkDiv == 0)
        sysInfo->pllFbkDiv = 16;

    /*
     * Determine CPU_DIV.
     */

    sysInfo->pllCpuDiv = 1 + ((pllmr0 & PLLMR0_CPU_DIV_MASK) >> PLLMR0_CPU_DIV_BIT_SHIFT);

    /*
     * Determine PLB_DIV.
     */

    sysInfo->pllPlbDiv = 1 + ((pllmr0 & PLLMR0_PLB_DIV_MASK) >> PLLMR0_PLB_DIV_BIT_SHIFT);

    /*
     * Determine OPB_DIV.
     */

    sysInfo->pllOpbDiv = 1 + ((pllmr0 & PLLMR0_OPB_DIV_MASK) >> PLLMR0_OPB_DIV_BIT_SHIFT);

    /*
     * Determine EXTBUS_DIV.
     */

    sysInfo->pllExtBusDiv = 2 + ((pllmr0 & PLLMR0_EBC_DIV_MASK) >> PLLMR0_EBC_DIV_BIT_SHIFT);

    /*
     * Determine PCI_DIV.
     */

    sysInfo->pllPciDiv = 1 + ((pllmr0 & PLLMR0_PCI_DIV_MASK) >> PLLMR0_PCI_DIV_BIT_SHIFT);

    /*
     * Determine MAL_DIV.
     */

    sysInfo->pllMalDiv = 1 + ((pllmr0 & PLLMR0_MAL_DIV_MASK) >> PLLMR0_MAL_DIV_BIT_SHIFT);

    /*
     * Calculate VCO frequency, processor frequency etc.
     *    spec:    VCO = SYS_CLOCK x FBKDIV x FWDBDIV
     * Note freqVCO is calculated in Mhz to avoid errors introduced by rounding.
     */

    multM = sysInfo->pllFwdBDiv * sysInfo->pllFbkDiv;

    sysInfo->freqVCOMhz = (1000 * multM) / sysClkPeriodNs;

    if (sysInfo->freqVCOMhz >= VCO_MIN && sysInfo->freqVCOMhz <= VCO_MAX)
        {

        sysInfo->freqPLLOUTA = (sysInfo->freqVCOMhz * 1000000)
                           / sysInfo->pllFwdADiv;

        sysInfo->freqProcessor = (sysInfo->freqVCOMhz * 1000000)
                           / (sysInfo->pllFwdADiv * sysInfo->pllCpuDiv);

        sysInfo->freqPLB = (sysInfo->freqVCOMhz * 1000000)
                           / (sysInfo->pllFwdADiv * sysInfo->pllCpuDiv
                               * sysInfo->pllPlbDiv);

        /*
         * The 405EP supports only an asychronous PCI clock.  This is a
         * SYNC_PCI_CLK needed inside the chip so the PCI bridge can
         * interface to the PLB bus.
         * The asynchronous PCI bus clock must follow this rule:
         *
         *   ((freqPCISync/2) + 1MHz) < async PCI clock <= (freqPCISync + 2MHz)
         *
         */

        sysInfo->freqPCISync = (sysInfo->freqVCOMhz * 1000000)
                           / (sysInfo->pllFwdADiv * sysInfo->pllCpuDiv
                               * sysInfo->pllPlbDiv * sysInfo->pllPciDiv);

        }
    else
        {
        if (verbose)
            {
            printf("Invalid VCO frequency calculated :  %d MHz \a\n",
                   sysInfo->freqVCOMhz);
            printf("It must be between %d-%d MHz \a\n", VCO_MIN, VCO_MAX);
            printf("PLL Mode reg 0         :  %8.8x\a\n", pllmr0);
            printf("PLL Mode reg 1         :  %8.8x\a\n", pllmr1);
            }
        return(ERROR);
        }


    /*
     * From the FPGA registers, determine the asynchronous PCI clock
     * being supplied to the board by the C9531.
     */

    switch (c9531Mult)
        {
        case 1 :
            sysInfo->freqPCI = 33333333;
            break;
       /******Add by lp,2004.10.18*******/
       /*  case 2 :
        case 4 :
            if (fpgaReg1 & FPGA_REG1_PCI_FREQ)
                sysInfo->freqPCI = 33333333;
            else
                sysInfo->freqPCI = 66666666;
            break;

        case 3 :
            if (fpgaReg1 & FPGA_REG1_PCI_FREQ)
                sysInfo->freqPCI = 25000000;
            else
                sysInfo->freqPCI = 50000000;
            break;*/

        default :
            printf("Can't determine PCI frequency\n");
            break;

        }

    /*
     * Output info.
     */

    if (verbose)
        {
        printf(" %s\n", sysModel());
        printf(" 405EP input       = %d MHz\n", sysInfo->freqInput/1000000);
        printf(" Processor speed   = %d MHz\n", sysInfo->freqProcessor/1000000);
        printf(" PLB speed         = %d MHz\n", sysInfo->freqPLB / 1000000);
        printf(" OPB speed         = %d MHz\n",
                           sysInfo->freqPLB / sysInfo->pllOpbDiv / 1000000);
        printf(" Ext Bus speed     = %d MHz\n",
                           sysInfo->freqPLB / sysInfo->pllExtBusDiv / 1000000);
        printf(" MAL speed         = %d MHz\n",
                           sysInfo->freqPLB / sysInfo->pllMalDiv / 1000000);

        printf(" SYNC_PCI_CLK      = %d MHz\n", sysInfo->freqPCISync / 1000000);
        printf(" PCI bus speed     = %d MHz\n", sysInfo->freqPCI / 1000000);
        }

    /*
     * Check the CPC0_PCI reg to determine if romInit enabled the
     * arbiters was enabled in romInit.s
     */

    if (sysDcrInLong(CPC0_PCI) & PCI_ARB_EN)
       {
       sysInfo->pciIntArbEn = TRUE;
       if (verbose)
           printf(" Internal PCI arbiter enabled\n\n");
       }
    else
       {
       sysInfo->pciIntArbEn = FALSE;
       if (verbose)
           printf(" External PCI arbiter enabled\n\n");
       }

    return(OK);
    }

#ifdef INCLUDE_SHOW_ROUTINES
/*******************************************************************************
*
* sysInfoShow - show system information (clock frequencies, etc.) based on
*               board switch and jumper settings.
*
* This routine displays information about the current operating environment of
* the board.
*
* RETURNS: OK or ERROR.
*/

STATUS sysInfoShow
    (
    )
    {
    SYS_INFO  sysInfo;

    return(sysInfoGet(&sysInfo, 1));

    }
#endif /* INCLUDE_SHOW_ROUTINES */

/*******************************************************************************
*
* debugLeds - set board LEDs to a value between 0 and 7.
*
* This routine sets the 3 debug LEDs on the board to the specified value.
*
* RETURNS: N/A
*/

void debugLeds
    (
    UINT value
    )
    {

    UCHAR fpga;

    if (value > 7)
        {
        printf("LED value must be between 0 and 7.\n");
        return;
        }

    /* Read FPGA register, add LED value desired, write back */
    fpga = sysInByte(FPGA_REG0);
    fpga = (fpga & (~FPGA_REG0_LED_MASK)) | (UCHAR)value;
    sysOutByte(FPGA_REG0, fpga);

    }