syslib.c.bak

移植好的Ibm405ep bsp板极支持包

* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
*
* RETURNS: A pointer to the string "IBM PowerPC 405EP Rev. x".
*/

char * sysModel (void)
    {

    if (vxPvrGet() == PVR_405EP)
        {
        if (sysDcrInLong(CPC0_JTAGID) == JTAGID_405EP_REVA)
            return ("IBM PowerPC 405EP Rev. A");
        if (sysDcrInLong(CPC0_JTAGID) == JTAGID_405EP_REVB)
            return ("IBM PowerPC 405EP Rev. B");
        return("IBM PowerPC 405EP Unknown version");
        }

    return ("Unknown processor");
    }

/*******************************************************************************
*
* sysBspRev - return the BSP version and revision number
*
* This routine returns a pointer to a BSP version and revision number, for
* example, 1.1/0.  BSP_REV is concatenated to BSP_VERSION and returned.
*
* RETURNS: A pointer to the BSP version/revision string.
*/

char * sysBspRev (void)
    {
    return (BSP_VERSION BSP_REV);
    }

/*******************************************************************************
*
* sysHwInit - initialize the system hardware
*
* This routine initializes various features of the IBM 405EP board. This
* routine clears and turns off the external interrupts.  It is called from
* usrInit() in usrConfig.c.
*
* NOTE: This routine should not be called directly by the user application.
*
* RETURNS: N/A
*/

void sysHwInit (void)
    {

#ifdef  INCLUDE_CACHE_SUPPORT
    UINT32  memSize;
    UINT32  cacheBit;
#endif /* INCLUDE_CACHE_SUPPORT */
  
    /* Fill in global system information structure */

    sysInfoGet(&systemInfo, FALSE);

    /* Set the 405 Exception Vector Prefix Register */

    vxEvprSet (EVPR_VAL_405);

    /* Interrupt system initialization */

    sysUicIntrInit ();

    /*
     * In 405EP, external timer clock is not supported, so timers always
     * run at the frequency of the CPU.
     */

    sysTimerClkFreq = systemInfo.freqProcessor;

    /*
     * Connect the UIC interrupt handler to both the external interrupt
     * and the critical interrupt sources.
     */

    excIntConnect ((VOIDFUNCPTR *) _EXC_OFF_INTR, sysUicIntHandler);
    excIntCrtConnect ((VOIDFUNCPTR *) _EXC_OFF_CRTL, sysUicIntHandler);

#ifdef INCLUDE_EMAC_NETWORK
    malReset(MAL0_DCR_BASE);
#endif


#ifdef INCLUDE_PCI

    /*
     * Initialize the PCI interrupt library, the PCI configuration library,
     * and the PCI bridge.
     */

    pciIntLibInit();
    pciConfigLibInit(PCI_MECHANISM_0, (ULONG)ibmPciConfigRead,
                     (ULONG)ibmPciConfigWrite, NULL);

    sysPciHostBridgeInit();

    /*
     * Initialize vendor ID of the 405EP (0x1014 is IBM).  The 405EP SEEPROM
     * can also be used to initialize the vendor ID and device ID.
     */

    ibmPciConfigWrite(PCI_HOST_BUS, PCI_HOST_DEVICE, PCI_HOST_FUNCTION,
                    PCI_CFG_VENDOR_ID, 2, 0x1014);

    /*
     * Set the bit in the CPC0_PCI register that allows other PCI devices
     * to access config registers in the 405EP.
     */

    sysDcrOutLong(CPC0_PCI, (sysDcrInLong(CPC0_PCI) | PCI_HOST_CFG_EN));

#endif

/* Perform auto-configuration of devices on the PCI bus  */

#ifdef INCLUDE_PCI_AUTOCONF
    sysPciAutoConfig();
#endif

#ifdef INCLUDE_NETWORK
    sysNetHwInit();             /* network interface */
#endif

    /* initialize the serial driver(s) */

#ifdef INCLUDE_SIO
    sysSerialHwInit ();
#endif  /* INCLUDE_SIO */

    /*
     * ppc405IccrVal and ppc405DccrVal define respectively the cachability
     * state of the total effective adress space at a 128 MB granularity
     * for instruction and data (in real mode). Start with the default
     * values, then turn on the appropriate number of bits in ICCR and
     * DCCR to correspond with the amount of SDRAM detected.
     */

#ifdef  INCLUDE_CACHE_SUPPORT

    /* Start with setting the bit that controls caching between 0 and 128MB */
    cacheBit = 0x80000000;
    ppc405IccrVal = _PPC405_ICCR_DEFAULT_VAL | cacheBit;
    ppc405DccrVal = _PPC405_DCCR_DEFAULT_VAL | cacheBit;

    /* If the SDRAM is larger than 128MB keep turning on bits */
    memSize = (UINT32)sysPhysMemTop();
    while (memSize > 0x08000000)
        {
        cacheBit = cacheBit >> 1;
        ppc405IccrVal |= cacheBit;
        ppc405DccrVal |= cacheBit;
        memSize -= 0x08000000;
        }

#endif	/* INCLUDE_CACHE_SUPPORT */
    
     #ifdef INCLUDE_LCD
       ca320240_init();
       ca320240DevInit1();
     #endif
    }

/*******************************************************************************
*
* sysHwInit2 - initialize additional system hardware
*
* This routine connects system interrupts and configures any required features
* not configured by sysHwInit().
*
* RETURNS: N/A
*/

void sysHwInit2 (void)
    {
    static BOOL configured = FALSE;

    if (!configured)
        {
        /* connect system clock interrupt : excIntConnectTimer uses malloc */

        excIntConnectTimer ((VOIDFUNCPTR *) _EXC_OFF_PIT,
                            (VOIDFUNCPTR) sysClkInt);

        /* connect auxiliary clock interrupt */

        excIntConnectTimer ((VOIDFUNCPTR *) _EXC_OFF_FIT,
                            (VOIDFUNCPTR) sysAuxClkInt);

#ifdef INCLUDE_NETWORK
        sysNetHwInit2 ();       /* network interface */
#endif

        /* connect serial interrupts */

#ifdef INCLUDE_SIO
        sysSerialHwInit2();
#endif

        configured = TRUE;
        }
    }


/*******************************************************************************
*
* sysPhysMemTop - get the address of the top of physical memory
*
* This routine returns the address of the first missing byte of memory,
* which indicates the top of memory.
*
* Normally, the user specifies the amount of physical memory with the
* macro LOCAL_MEM_SIZE in config.h.  BSPs that support run-time
* memory sizing do so only if the macro LOCAL_MEM_AUTOSIZE is defined.
* If not defined, then LOCAL_MEM_SIZE is assumed to be, and must be, the
* true size of physical memory.
*
* NOTE: Do not adjust LOCAL_MEM_SIZE to reserve memory for application
* use.  See sysMemTop() for more information on reserving memory.
*
* RETURNS: The address of the top of physical memory.
*
* SEE ALSO: sysMemTop()
*/

char * sysPhysMemTop (void)
    {
    static char * physTop = NULL;
#ifdef LOCAL_MEM_AUTOSIZE
    UINT32 sdramBankCfg[2];        /* only 2 SDRAM banks on 405EP */
    int          memBank;
#endif

    if (physTop == NULL)
        {
#ifdef LOCAL_MEM_AUTOSIZE

        /* Read both of the SDRAM controller bank control registers */

        sysDcrOutLong(SDRAM0_CFGADDR, SDRAM_B0CR);
        sdramBankCfg[0] = sysDcrInLong(SDRAM0_CFGDATA);

        sysDcrOutLong(SDRAM0_CFGADDR, SDRAM_B1CR);
        sdramBankCfg[1] = sysDcrInLong(SDRAM0_CFGDATA);

        /*
         * Check each of the SDRAM banks in the controller. If a bank is
         * enabled get the size it is configured to and add to the total.
         */

        for (memBank = 0; memBank < NELEMENTS(sdramBankCfg); memBank++)
            {
            if (sdramBankCfg[memBank] & SDRAM_BXCR_SDX_BE)
                {
                switch(sdramBankCfg[memBank] & SDRAM_BXCR_SDX_SZ)
                    {
                    case SDRAM_BXCR_SDX_SZ_4:
                        physTop = (char *)(4 * 1024 * 1024);           /* 4MB */
                        break;
                    case SDRAM_BXCR_SDX_SZ_8:
                        physTop = physTop + (8 * 1024 * 1024);         /* 8MB */
                        break;
                    case SDRAM_BXCR_SDX_SZ_16:
                        physTop = physTop + (16 * 1024 * 1024);       /* 16MB */
                        break;
                    case SDRAM_BXCR_SDX_SZ_32:
                        physTop = physTop + (32 * 1024 * 1024);       /* 32MB */
                        break;
                    case SDRAM_BXCR_SDX_SZ_64:
                        physTop = physTop + (64 * 1024 * 1024);       /* 64MB */
                        break;
                    case SDRAM_BXCR_SDX_SZ_128:
                        physTop = physTop + (128 * 1024 * 1024);     /* 128MB */
                        break;
                    case SDRAM_BXCR_SDX_SZ_256:
                        physTop = physTop + (256 * 1024 * 1024);     /* 256MB */
                        break;
                    case SDRAM_BXCR_SDX_SZ_512:
                        physTop = physTop + (512 * 1024 * 1024);     /* 512MB */
                        break;
                    }
                }
            }

    /*
     * based on the size of the memory we calculated, update the sysPhysMemDesc
     * structure, so that we map the right size of RAM.
     * We assume that the first element in the sysPhysMemDesc structure is
     * referring to RAM.
     */
    sysPhysMemDesc[0].len = (UINT32)physTop - LOCAL_MEM_LOCAL_ADRS;


#else /*LOCAL_MEM_AUTOSIZE*/

        /* Don't do autosizing, size is given */

        physTop = (char *)(LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE);
      

#endif /*LOCAL_MEM_AUTOSIZE*/
        }

    return physTop;
    }

/*******************************************************************************
*
* sysMemTop - get the address of the top of VxWorks memory
*
* This routine returns a pointer to the first byte of memory not
* controlled or used by VxWorks.
*
* The user can reserve memory space by defining the macro USER_RESERVED_MEM
* in config.h.  This routine returns the address of the reserved memory
* area.  The value of USER_RESERVED_MEM is in bytes.
*
* RETURNS: The address of the top of VxWorks memory.
*/

char * sysMemTop (void)
    {
    static char * memTop = NULL;

    if (memTop == NULL)
        {
        memTop = sysPhysMemTop () - USER_RESERVED_MEM;
        }

    return memTop;
    }

/********************************************************************************
*
* sysToMonitor - transfer control to the ROM monitor
*
* This routine transfers control to the ROM monitor.  Normally, it is called
* only by reboot()--which services ^X--and by bus errors at interrupt level.
* However, in special circumstances, the user may wish to introduce a
* <startType> to enable special boot ROM facilities.
*
* RETURNS: Does not return.
*/

STATUS sysToMonitor
    (
    int startType    /* parameter passed to ROM to tell it how to boot */
    )
    {
    FUNCPTR pRom = (FUNCPTR) (ROM_TEXT_ADRS + 4); /* Warm reboot */

    cacheDisable (0);			/* disable icache */
    cacheDisable (1);			/* disable dcache */

    sysDcrOutLong(UIC0_SR, 0xFFFFFFFF); /* clear pending interrupts */

    vxMsrSet (0);		/* clear MSR */

    (*pRom) (startType);        /* jump to bootrom */

    return (OK);                /* in case we ever continue from ROM monitor */
    }

/*******************************************************************************
*
* sysProcNumGet - get the processor number
*
* This routine returns the processor number for the CPU board, which is
* set with sysProcNumSet().
*
* RETURNS: The processor number for the CPU board, always 0 (zero).
*
* SEE ALSO: sysProcNumSet()
*/

int sysProcNumGet (void)
    {
    return (0);
    }

/*******************************************************************************