syslib.c.bak

移植好的Ibm405ep bsp板极支持包

/* sysLib.c - IBM 405EP eval board (ibmEvb405EP) system-dependent routines */

/*******************************************************************************
   This source and object code has been made available to you by IBM on an
   AS-IS basis.

   IT IS PROVIDED WITHOUT WARRANTY OF ANY KIND, INCLUDING THE WARRANTIES OF
   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE OR OF NONINFRINGEMENT
   OF THIRD PARTY RIGHTS.  IN NO EVENT SHALL IBM OR ITS LICENSORS BE LIABLE
   FOR INCIDENTAL, CONSEQUENTIAL OR PUNITIVE DAMAGES.  IBM芐 OR ITS LICENSOR芐
   DAMAGES FOR ANY CAUSE OF ACTION, WHETHER IN CONTRACT OR IN TORT, AT LAW OR
   AT EQUITY, SHALL BE LIMITED TO A MAXIMUM OF $1,000 PER LICENSE.  No license
   under IBM patents or patent applications is to be implied by the copyright
   license.

   Any user of this software should understand that neither IBM nor its
   licensors will be responsible for any consequences resulting from the use
   of this software.

   Any person who transfers this source code or any derivative work must
   include the IBM copyright notice, this paragraph, and the preceding two
   paragraphs in the transferred software.

   Any person who transfers this object code or any derivative work must
   include the IBM copyright notice in the transferred software.

   COPYRIGHT   I B M   CORPORATION 2000
   LICENSED MATERIAL  -  PROGRAM PROPERTY OF  I B M"

*******************************************************************************/

/* Copyright 1984-2001 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01l,06sep02,mcg  add support for 405EP rev 1.1 (rev B)
01k,11jul02,mcg  fix ICCR and DCCR initialization when more than 128MB of SDRAM
                 is detected. Converted for ibmEvb405EP.
01j,05sep01,kab  grouped all sys[In|Out]* funcs in sysALib.s
01k,27jul01,kab  fixed sysToMonitor (SPR 68699); cleanup
01j,06dec00,s_m  changed sysModel to handle Rev E
01i,27nov00,s_m  moved END and timer drivers back to bsp dir
01h,23oct00,s_m  fixed comment
01g,23oct00,s_m  fixed CPU comment
01f,23oct00,s_m  added comment for sysPhysMemDesc
01e,25may00,mcg  added sysInfoGet() and sysInfoShow()
01d,11may00,mcg  removed PCI configuration code added calls to VxWorks
                 PCI autoconfiguration code
01c,29mar00,mcg  moved sysTimerClkFreq initialization to the beginning of
                 sysHwInit to fix sysLocalDelay
01b,22jan00,mcg  added LOCAL_MEM_AUTOSIZE support and RTC support
01a,20sep99,mcg  created from 403evb version 02e.
*/

/*
DESCRIPTION
This library provides board-specific routines.   The chip drivers included are:

.IP "uicIntr.c"
On-chip Universal Interrupt Controller library.
.IP "d1643RTC.c"
Driver for the real time clock portion of the Dallas Semiconductor DS1643
Nonvolative Timekeeping RAM.
.IP "pci/pciConfigLib.c"
PCI Configuration space access support for PCI drivers
.IP "pci/pciIntLib.c"
PCI Shared Interrupt support
.IP "pci/pciConfigShow.c"
Show routines of PCI bus(IO mapped) library
.IP "pci/pciAutoConfigLib.c"
PCI bus scan and resource allocation facility
.IP "malLib.c"
IBM Memory Access Layer (MAL) library
.IP "ibmEmacEnd.c"
END style driver for IBM EMAC Ethernet
.IP "ibmDma.c"
IBM DMA controller driver

INCLUDE FILES: sysLib.h

SEE ALSO:
.pG "Configuration"
*/

/* includes */

#include "vxWorks.h"
#include "cacheLib.h"
#include "asm.h"
#include "vme.h"
#include "iv.h"
#include "esf.h"
#include "ioLib.h"
#include "sysLib.h"
#include "config.h"
#include "memLib.h"
#include "excLib.h"
#include "logLib.h"
#include "vxLib.h"
#include "string.h"
#include "intLib.h"
#include "taskLib.h"
#include "private/vmLibP.h"
#include "ppc405EP.h"

#ifdef INCLUDE_NC3016_SST
#include "flash/nc3016_sst.c"
#endif

#ifdef INCLUDE_AM29LV160MB
#include "flash/am29lv160mb.c"
#endif
#ifdef INCLUDE_AM29LV320MB
#include "flash/am29lv320mb.c"
#endif
#include "flash/nc3016_boot.c"
#include "flash/server_flash.c"


#include "ca320240/ca320240.c"
#include "ca320240/ca320240_drv.c"
#include "ca320240/6x12-iso8859-1.c"
#include "ca320240/song-12-gb2312.c"

/* externals */

IMPORT STATUS   excIntConnectTimer (VOIDFUNCPTR * vector, VOIDFUNCPTR routine);
IMPORT void     excIntHandle (void);
IMPORT UINT32   ppc405IccrVal;          /* cachability state for instruction */
IMPORT UINT32   ppc405DccrVal;          /* cachability state for data */

/* globals */

int   sysBus;                           /* system bus type (VME_BUS, etc) */
int   sysCpu      = CPU;                /* system CPU type */
char *sysBootLine = BOOT_LINE_ADRS;     /* address of boot line */
char *sysExcMsg   = EXC_MSG_ADRS;       /* catastrophic message area */
int   sysFlags;                         /* boot flags */
char  sysBootHost [BOOT_FIELD_LEN];     /* name of host from which we booted */
char  sysBootFile [BOOT_FIELD_LEN];     /* name of file from which we booted */
int   sysTimerClkFreq;                  /* Timer clock frequency             */
SYS_INFO systemInfo;                    /* PLL and system frequencies        */

/* The following variables specify the cache line size and the number of
 * cache lines for the 405EP. These are used by the architecture cache
 * libraries.
 */
const int  ppc405ICACHE_LINE_NUM = _ICACHE_LINE_NUM_405EP;			
												/* no. of lines in ICACHE */
const int  ppc405DCACHE_LINE_NUM = _DCACHE_LINE_NUM_405EP;			
												/* no. of lines in DCACHE */
const int  ppc405CACHE_ALIGN_SIZE = _CACHE_ALIGN_SIZE;			
												/* cache line size */

/*
 * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
 * used by the MMU to translate addresses with single page (4k) granularity.
 *
 * Address translations for local RAM, memory mapped PCI bus, memory mapped
 * IO space and local PROM/FLASH are set here.
 *
 * PTEs are held in a 2-level page table. There is one Level 1 page table
 * and several Level 2 page tables. The size of the Level 1 table is 4K
 * and the size of each Level 2 page table is 8K. Each Level 2 table can
 * map upto 4MB of contiguous memory space.
 *
 * Calculating size of page table required:
 * =======================================
 * For the following memory map we can calculate the page table size
 * required as follows:
 *
 *	Memory Area				Size				# of Level 2 pages
 *	===========				====				==================
 *	1. Local Memory			32MB						8
 *	2. PCI Memory			64MB					    16
 *	3. PCI IO Regn 1		64K							1
 * 	4. PCI IO Regn 2		1MB							1
 *	5. PCI CFG				4K							1
 * 	6. PCI IACK				4K							0 @
 *	7. PP Bridge			4K							1
 * 	8. UART IO Space		4K							0 @
 *	9. NVRAM Space			8K							1
 *	10. Flash				512K						1
 *	@ - included in previous L2 page
 *
 *	Total # of L2 pages =								30
 *	Total Memory Required for page table = 30 * 8 + 4 = 244 K.
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
    {
    {
    (void *) LOCAL_MEM_LOCAL_ADRS,
    (void *) LOCAL_MEM_LOCAL_ADRS,
    LOCAL_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE
    },

   /* {
    (void *) LOCAL_MEM_LOCAL_ADRS1,
    (void *) LOCAL_MEM_LOCAL_ADRS1,
    LOCAL_MEM_SIZE1,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE 
    },   */

    {
    (void *) PCI_MEMORY_START,
    (void *) PCI_MEMORY_START,
    PCI_MEMORY_MAP_END - PCI_MEMORY_START + 1,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

    {
    (void *) PLB_PCI_IO_REGION_1_START,
    (void *) PLB_PCI_IO_REGION_1_START,
    PLB_PCI_IO_REGION_1_END - PLB_PCI_IO_REGION_1_START + 1,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

    {
    (void *) PLB_PCI_IO_REGION_2_START,
    (void *) PLB_PCI_IO_REGION_2_START,
    PLB_PCI_IO_REGION_2_MAP_END - PLB_PCI_IO_REGION_2_START + 1,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

    {
    (void *) PCI_CFGADDR,
    (void *) PCI_CFGADDR,
    PCI_CFGEND - PCI_CFGADDR + 1,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

    {
    (void *) PCI_INTERRUPT_ACK,
    (void *) PCI_INTERRUPT_ACK,
    PCI_INTERRUPT_ACK_END - PCI_INTERRUPT_ACK + 1,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

    {
    (void *) PP_BRIDGE_CR,
    (void *) PP_BRIDGE_CR,
    PP_BRIDGE_CR_END - PP_BRIDGE_CR + 1,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

    {
    (void *) UART_MEMORY_START,
    (void *) UART_MEMORY_START,
    UART_MEMORY_END - UART_MEMORY_START + 1,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

    {
    (void *) NV_RAM_ADRS,
    (void *) NV_RAM_ADRS,
    NV_RAM_SIZE_ALIGNED,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },

   /* {
    (void *) FPGA_BASE_ADRS,
    (void *) FPGA_BASE_ADRS,
    4*1024,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |
    VM_STATE_GUARDED
    },*/

    {
    (void *) FLASH_START,
    (void *) FLASH_START,
    FLASH_END - FLASH_START + 1,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },
    
    {
    (void *) FLASH_BASE_ADRS1,
    (void *) FLASH_BASE_ADRS1,
    FLASH_SIZE1,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },
    
    {
    (void *) FLASH_BASE_ADRS2,
    (void *) FLASH_BASE_ADRS2,
    FLASH_SIZE2,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },
    #ifdef INCLUDE_LCD
    {
    (void *) CA0320240_ADDR,
    (void *) CA0320240_ADDR,
    0x100000,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },
    #endif
    };

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

/* forward declarations */

STATUS sysInfoGet(SYS_INFO * sysInfo, int verbose);
void   sysLocalDelay(UINT32 ms_delay);

UCHAR  sysPciInByte(ULONG address);
void   sysPciOutByte(ULONG address, UCHAR data);
UINT16 sysPciInWord(ULONG address);
void   sysPciOutWord(ULONG address, UINT16 data);
UINT   sysPciInLong(ULONG address);
void   sysPciOutLong(ULONG address, UINT data);
void   debugLeds(UINT value);


/* locals */

LOCAL int sysProcNum;                   /* processor number of this CPU */

#ifdef DOC
#define INCLUDE_TIMESTAMP
#endif

/* BSP Drivers */

#include "mem/byteNvRam.c"
#include "vme/nullVme.c"
#include "uicIntr.c"                    /* UIC interrupt library */
#include "ppc405Timer.c"                /* ppc405 timer driver */
#include "sysSerial.c"
#include "ibmDma.c"                     /* IBM DMA controller driver */

#ifdef INCLUDE_PCI
#   include "pci/pciConfigLib.c"
#   include "pci/pciIntLib.c"
#   include "pci/pciConfigShow.c"
#   ifdef INCLUDE_PCI_AUTOCONF
#       include "pci/pciAutoConfigLib.c"
#       include "sysBusPci.c"
#   endif
#endif

#include "sysNet.c"
#ifdef INCLUDE_EMAC_NETWORK
#  include "malLib.c"
#  include "ibmEmacEnd.c"
#endif
#ifdef INCLUDE_RTC
#include "d1643RTC.c"                   /* Real Time Clock */
#endif

/*******************************************************************************
*