sysalib.s

移植好的Ibm405ep bsp板极支持包

/* sysALib.s - IBM ibmEvb405EP system-dependent assembly routines */

/*******************************************************************************
   This source and object code has been made available to you by IBM on an
   AS-IS basis.

   IT IS PROVIDED WITHOUT WARRANTY OF ANY KIND, INCLUDING THE WARRANTIES OF
   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE OR OF NONINFRINGEMENT
   OF THIRD PARTY RIGHTS.  IN NO EVENT SHALL IBM OR ITS LICENSORS BE LIABLE
   FOR INCIDENTAL, CONSEQUENTIAL OR PUNITIVE DAMAGES.  IBM芐 OR ITS LICENSOR芐
   DAMAGES FOR ANY CAUSE OF ACTION, WHETHER IN CONTRACT OR IN TORT, AT LAW OR
   AT EQUITY, SHALL BE LIMITED TO A MAXIMUM OF $1,000 PER LICENSE.  No license
   under IBM patents or patent applications is to be implied by the copyright
   license.

   Any user of this software should understand that neither IBM nor its
   licensors will be responsible for any consequences resulting from the use
   of this software.

   Any person who transfers this source code or any derivative work must
   include the IBM copyright notice, this paragraph, and the preceding two
   paragraphs in the transferred software.

   Any person who transfers this object code or any derivative work must
   include the IBM copyright notice in the transferred software.

   COPYRIGHT   I B M   CORPORATION 2000
   LICENSED MATERIAL  -  PROGRAM PROPERTY OF  I B M"

*******************************************************************************/

/* Copyright 1984-1999 Wind River Systems, Inc. */
/* .globl       _copyright_wind_river */

/*
modification history
--------------------
01h,11jul01,mcg  Removed include of uicDcr.s, dmaDcr.s, ebcDcr.s.  All
                 DCR accesses now done through sysDcr.s.  For ibmEvb405EP.
01g,05sep01,kab  grouped all sys[In|Out]* funcs here
01f,04dec00,s_m  used cache size defines from ppc405GP.h
01e,23oct00,s_m  changes for new kernel cache support
01d,25aug00,mcg  disable caches upon entry
01c,15may00,mcg  register name updates to match 405GP User Manual
01b,28mar00,mcg  change register init to reflect changes to romInit
                 added cache initialization
01a,31aug99,mcg  created from evb403 version 01r.
*/

/*
DESCRIPTION
This module contains system-dependent routines written in assembly
language.

This module must be the first specified in the \f3ld\f1 command used to
build the system.  The sysInit() routine is the system start-up code.
*/

#define _ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "config.h"
#include "asm.h"
#include "regs.h"

        /* globals */

        .globl  FUNC(_sysInit)                  /* start of system code */
        FUNC_DECL(.globl, _sysInit)
        .globl  sysPciInByte
        FUNC_DECL(.globl, sysPciInByte)
        .globl  sysPciOutByte
        FUNC_DECL(.globl, sysPciOutByte)
        .globl  sysPciInWord
        FUNC_DECL(.globl, sysPciInWord)
        .globl  sysPciOutWord
        FUNC_DECL(.globl, sysPciOutWord)
        .globl  sysPciInLong
        FUNC_DECL(.globl, sysPciInLong)
        .globl  sysPciOutLong
        FUNC_DECL(.globl, sysPciOutLong)
        .globl  sysInByte
        FUNC_DECL(.globl, sysInByte)
        .globl  sysOutByte
        FUNC_DECL(.globl, sysOutByte)
        .globl  sysInWord
        FUNC_DECL(.globl, sysInWord)
        .globl  sysOutWord
        FUNC_DECL(.globl, sysOutWord)
        .globl  sysInLong
        FUNC_DECL(.globl, sysInLong)
        .globl  sysOutLong
        FUNC_DECL(.globl, sysOutLong)
        .globl  sysSpin
        FUNC_DECL(.globl, sysSpin)

        .globl  FUNC(sysDcrPlbbesrGet)
        FUNC_DECL(.globl, sysDcrPlbbesrGet)
        .globl  FUNC(sysDcrPlbbesrClear)
        FUNC_DECL(.globl, sysDcrPlbbesrClear)
        .globl  FUNC(sysDcrPlbbearGet)
        FUNC_DECL(.globl, sysDcrPlbbearGet)

        /* externals */

        .extern FUNC(usrInit)

        .text


/*******************************************************************************
*
* sysInit - start after boot
*
* This routine is the system start-up entry point for VxWorks in RAM, the
* first code executed after booting.  It disables interrupts, sets up the
* stack, and jumps to the C routine usrInit() in usrConfig.c.
*
* The initial stack is set to grow down from the address of sysInit().  This
* stack is used only by usrInit() and is never used again.  Memory for the
* stack must be accounted for when determining the system load address.
*
* NOTE: This routine should not be called by the user.
*
* RETURNS: N/A

* sysInit (void)        /@ THIS IS NOT A CALLABLE ROUTINE @/

*/

_sysInit:


        /* Repeat initialization done in romInit.s except SDRAM and EBC */


        /*
         * Initalize registers that need to be set to zero.
         */

        addi    r4,r0,0x0000
        mtmsr   r4                      /* disable all interrupts        */
        isync
        mtspr   ICCR,r4                 /* turn off I-cache              */
        mtspr   DCCR,r4                 /* turn off D-cache              */
        mtspr   DCWR,r4                 /* all memory regions write-back */
        mtspr   ESR, r4                 /* clear error status            */
        mtspr   TCR, r4                 /* disable all timers            */
        mtspr   PIT, r4                 /* clear the PIT timer           */
        mtdcr   UIC0_ER, r4             /* disable ints at the UIC       */
        mtspr   XER, r4                 /* clear integer exception reg   */
        mtdcr   DMA0_CR0, r4            /* stop DMA channels             */
        mtdcr   DMA0_CR1, r4
        mtdcr   DMA0_CR2, r4
        mtdcr   DMA0_CR3, r4

        /*
         * Initalize registers that need to be cleared with 0xFFFFFFFF
         */

        addis   r4,r0,0xffff
        ori     r4,r4,0xffff
        mtspr   TSR, r4                 /* clear timer status            */
        mtspr   DBSR, r4                /* clear debug status reg        */
        mtdcr   UIC0_SR, r4             /* clear all pending UIC ints    */
        mtdcr   DMA0_SR, r4             /* clear DMA status reg          */

        /*
         * Set storage guarded attribute
         *     Unguarded: 0x00000000 - 0x7FFFFFFF  SDRAM
         *       Guarded: 0x80000000 - 0xF7FFFFFF  PCI Memory, I/O, config,
         *                                         405EP internal peripherals,
         *                                         external peripherals
         *     Unguarded: 0xF8000000 - 0xFFFFFFFF  Bootrom
         */

        addi    r4,r0,0x0000
        ori     r4,r4,0xfffe
        mtspr   SGR,r4

        /*
         * Invalidate the entire instruction cache. This can be done
         * with a single iccci instruction in the 405 processor core.
         */

        iccci   r0, r0

        /*
         * Invalidate the entire data cache.
         * The 405 processor core in the 405EP has 256 congruence classes.
         * Each cache line in the 405 processor is 32 bytes.
         */

        li      r3, 0                     /* clear r3 */
        li      r4, _DCACHE_LINE_NUM_405EP   /* load number of cache lines */
        mtctr   r4

rom403Dcci:
        dccci   r0, r3
        addi    r3, r3, _CACHE_ALIGN_SIZE       /* bump to next line */
        bdnz    rom403Dcci                      /* go to invalidate */

        /*
         * Clear the CPU reservation bit
         */

        li      r0, 0
        lwarx   r3, r0, r0
        stwcx.  r3, r0, r0

        /*
         * Initialize the stack pointer
         */

        lis     sp, HIADJ(_sysInit)
        addi    sp, sp, LO(_sysInit)

#if     FALSE                           /* SDA not supported */
        /* initialize r2 and r13 according to EABI standard */

        lis     r2, HIADJ(_SDA2_BASE_)
        addi    r2, r2, LO(_SDA2_BASE_)
        lis     r13, HIADJ(_SDA_BASE_)
        addi    r13, r13, LO(_SDA_BASE_)
#endif

        mfmsr   r3                      /* read msr */
        INT_MASK(r3, r3)                /* mask ee bit and ce bit */
        mtmsr   r3                      /* DISABLE INTERRUPT */

        addi    sp, sp, -FRAMEBASESZ    /* car frame stack */
        li      r3, BOOT_WARM_AUTOBOOT  /* set start type arg = WARM_BOOT */
        bl      FUNC(usrInit)

/*****************************************************************************
*
* sysPciInByte - reads a byte from PCI Config Space.
*
* This function reads a byte from a specified PCI Config Space address.
*
* ARGUMENTS:
*       r3      = Config Space address
*
* RETURNS:
*       r3      = byte from address.
*/

sysPciInByte:

        lbzx    r3,r0,r3        /* Read byte from PCI space */
        sync                    /* Sync I/O operation */
        bclr    20,0            /* Return to caller */

/*****************************************************************************
*
* sysPciInWord - reads a word (16-bit big-endian) from PCI Config Space.
*
* This function reads a word from a specified PCI Config Space (little-endian)
* address.  It uses the load halfword byte-reversed instruction.
*
* ARGUMENTS:
*       r3      = Config Space address
*
* RETURNS:
*       r3      = word (16-bit big-endian) from address.
*/