config.h

移植好的Ibm405ep bsp板极支持包

/* config.h - IBM 405EP eval board configuration header */

/*******************************************************************************
   This source and object code has been made available to you by IBM on an
   AS-IS basis.

   IT IS PROVIDED WITHOUT WARRANTY OF ANY KIND, INCLUDING THE WARRANTIES OF
   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE OR OF NONINFRINGEMENT
   OF THIRD PARTY RIGHTS.  IN NO EVENT SHALL IBM OR ITS LICENSORS BE LIABLE
   FOR INCIDENTAL, CONSEQUENTIAL OR PUNITIVE DAMAGES.  IBMS OR ITS LICENSORS
   DAMAGES FOR ANY CAUSE OF ACTION, WHETHER IN CONTRACT OR IN TORT, AT LAW OR
   AT EQUITY, SHALL BE LIMITED TO A MAXIMUM OF $1,000 PER LICENSE.  No license
   under IBM patents or patent applications is to be implied by the copyright
   license.

   Any user of this software should understand that neither IBM nor its
   licensors will be responsible for any consequences resulting from the use
   of this software.

   Any person who transfers this source code or any derivative work must
   include the IBM copyright notice, this paragraph, and the preceding two
   paragraphs in the transferred software.

   Any person who transfers this object code or any derivative work must
   include the IBM copyright notice in the transferred software.

   COPYRIGHT   I B M   CORPORATION 2000
   LICENSED MATERIAL  -  PROGRAM PROPERTY OF  I B M"

*******************************************************************************/

/*
modification history
--------------------
01n,20aug01,kab  Change ibmEmac to emac - max 4 letter boot dev in DHCP, other
01m,27jul01,kab  Remove 403_ON_405; bump BSP_REV
01l,18dec00,s_m  undefined PPC405GP_REVE
01k,06dec00,s_m  added define for Rev E
01j,05dec00,s_m  uses external clock by default as this allows variable baud
                 rates
01i,29nov00,s_m  updates from ibm
01h,20nov00,s_m  changed BSP_REV to 5
01g,14nov00,s_m  don't include IMMU enable by default
01f,28nov00,mcg  fixed comments regarding ROM/SRAM switch 6 on bank U79
01e,24aug00,mcg  added PCI master window for VGA cards
01d,09may00,mcg  added information for PCI autoconfig
01c,28mar00,mcg  update for revision 2 of the Walnut BSP
01b,02feb00,mcg  update for revision 1 of the Walnut BSP
01a,08sep99,mcg  created from evb403 config.h version 01v.
*/

/*
This file contains the configuration parameters for the
IBM 405EP evaluation board.
*/

#ifndef INCconfigh
#define INCconfigh

/* BSP version/revision identification, before configAll.h */
#define BSP_VER_1_2     1
#define BSP_VER_1_1     1
#define BSP_VERSION     "2.2"           /* A Tornado 2.0 BSP    */
#define BSP_REV         "/0"            /* 0 for first revision */

#include "configAll.h"


/*
 * Default boot line
 */

#define DEFAULT_BOOT_LINE \
    "emac(0,0)host:vxWorks h=192.168.3.119 e=192.168.3.118 u=target2 pw=ff"
    
#define INCLUDE_LCD
#define INCLUDE_SYSTEM_BOOT_PARA

#if 1
#define INCLUDE_LCD
#define INCLUDE_SYSTEM_BOOT_PARA
#endif

#undef CONSOLE_TTY

#ifndef INCLUDE_SYSTEM_BOOT_PARA
	#define	CONSOLE_TTY		0			/* console channel					*/
#else
	#define	CONSOLE_TTY		1			/* console channel*/
#endif 


#undef CONSOLE_BAUD_RATE
#define CONSOLE_BAUD_RATE	19200	/* console baud rate				*/

/*
 * Memory configuration.
 * SDRAM size is determined at boot time if LOCAL_MEM_AUTOSIZE is defined
 */

/*#define LOCAL_MEM_AUTOSIZE              */        /* run-time memory sizing     */
#define LOCAL_MEM_LOCAL_ADRS  0x00000000
#define LOCAL_MEM_SIZE        0x02000000   
#define USER_RESERVED_MEM     0                 /* see sysMemTop()            */
#define IBM405EP

/*
 * Select one of the CPU speeds below.
 */

#undef  CPU_SPEED_200
#define CPU_SPEED_266
#undef  CPU_SPEED_133

#if ((defined(CPU_SPEED_200) && defined(CPU_SPEED_266)) || \
     (defined(CPU_SPEED_200) && defined(CPU_SPEED_133)) || \
     (defined(CPU_SPEED_266) && defined(CPU_SPEED_133)))
#    error "Error:  Define only one CPU_SPEED macro."
#endif


/*
 * CPC0_PLLMR0 and CPC0_PLLMR1 settings for CPU=200MHz, PLB=100MHz
 *
 *     Assumes:  C9531 input  = 33MHz    C9531 multiplier = 1
 *       (jumpers J22 and J24 are installed)
 *
 *     FWDA divider = 2   FWDA frequency = 400MHz
 *     FWDB divider = 2   FWDB frequency = 400MHz
 *     FDBK divider = 12
 *     M = 24             VCO frequency = 800MHz
 *     CPUDIV = 2         CPU frequency = 200MHz
 *     PLBDIV = 2         PLB frequency = 100MHz
 *     OPBDIV = 2         OPB frequency = 50MHz
 *     EBCDIV = 2         EBC frequency = 50MHz
 *     MALDIV = 1         MAL frequency = 100MHz
 *     PCIDIV = 3         PCI frequency = 33MHz
 */

#define PLLMR0_200_100_50  (PLLMR0_CPU_DIV_2 | PLLMR0_PLB_DIV_2 |  \
                            PLLMR0_OPB_DIV_2 | PLLMR0_EBC_DIV_2 |  \
                            PLLMR0_MAL_DIV_1 | PLLMR0_PCI_DIV_3)

#define PLLMR1_200_100_50  (PLLMR1_PLL_ENGAGE | PLLMR1_FB_DIV_12  |  \
                            PLLMR1_FWDA_DIV_2 | PLLMR1_FWDB_DIV_2 |  \
                            PLLMR1_TUNE_15_M_40 | PLLMR1_TUNE_VCO_LOW)


/*
 * CPC0_PLLMR0 and CPC0_PLLMR1 settings for CPU=266MHz, PLB=133MHz
 *
 *     Assumes:  C9531 input  = 33MHz    C9531 multiplier = 1
 *       (jumpers J22 and J24 are installed)
 *
 *     FWDA divider = 3   FWDA frequency = 266MHz
 *     FWDB divider = 3   FWDB frequency = 266MHz
 *     FDBK divider = 8
 *     M = 24             VCO frequency = 800MHz
 *     CPUDIV = 1         CPU frequency = 266MHz
 *     PLBDIV = 2         PLB frequency = 133MHz
 *     OPBDIV = 2         OPB frequency = 66MHz
 *     EBCDIV = 2         EBC frequency = 66MHz
 *     MALDIV = 1         MAL frequency = 133MHz
 *     PCIDIV = 4         PCI frequency = 33MHz
 */

#define PLLMR0_266_133_66  (PLLMR0_CPU_DIV_1 | PLLMR0_PLB_DIV_2 |  \
                            PLLMR0_OPB_DIV_2 | PLLMR0_EBC_DIV_2 |  \
                            PLLMR0_MAL_DIV_1 | PLLMR0_PCI_DIV_4)

#define PLLMR1_266_133_66  (PLLMR1_PLL_ENGAGE | PLLMR1_FB_DIV_8   |  \
                            PLLMR1_FWDA_DIV_3 | PLLMR1_FWDB_DIV_3 |  \
                            PLLMR1_TUNE_15_M_40 | PLLMR1_TUNE_VCO_LOW)

/*
 * CPC0_PLLMR0 and CPC0_PLLMR1 settings for CPU=133MHz, PLB=133MHz
 *
 *     Assumes:  C9531 input  = 33MHz    C9531 multiplier = 1
 *       (jumpers J22 and J24 are installed)
 *
 *     FWDA divider = 7   FWDA frequency = 133MHz
 *     FWDB divider = 7   FWDB frequency = 133MHz
 *     FDBK divider = 4
 *     M = 28             VCO frequency = 933MHz
 *     CPUDIV = 1         CPU frequency = 133MHz
 *     PLBDIV = 1         PLB frequency = 133MHz
 *     OPBDIV = 2         OPB frequency = 66MHz
 *     EBCDIV = 2         EBC frequency = 66MHz
 *     MALDIV = 1         MAL frequency = 133MHz
 *     PCIDIV = 4         PCI frequency = 33MHz
 */

#define PLLMR0_133_133_66  (PLLMR0_CPU_DIV_1 | PLLMR0_PLB_DIV_1 |  \
                            PLLMR0_OPB_DIV_2 | PLLMR0_EBC_DIV_2 |  \
                            PLLMR0_MAL_DIV_1 | PLLMR0_PCI_DIV_4)

#define PLLMR1_133_133_66  (PLLMR1_PLL_ENGAGE | PLLMR1_FB_DIV_4   |  \
                            PLLMR1_FWDA_DIV_7 | PLLMR1_FWDB_DIV_7 |  \
                            PLLMR1_TUNE_15_M_40 | PLLMR1_TUNE_VCO_HI)

/*
 * Set PLLMR_SETTING to one of the configurations above.
 */
#if defined (CPU_SPEED_200)
#    define PLLMR0_SETTING   PLLMR0_200_100_50
#    define PLLMR1_SETTING   PLLMR1_200_100_50
#elif defined (CPU_SPEED_266)
#    define PLLMR0_SETTING   PLLMR0_266_133_66
#    define PLLMR1_SETTING   PLLMR1_266_133_66
#    define SDRAM_133
#elif defined (CPU_SPEED_133)
#    define PLLMR0_SETTING   PLLMR0_133_133_66
#    define PLLMR1_SETTING   PLLMR1_133_133_66
#    define SDRAM_133
#else
#    error "Error:  Define a CPU_SPEED macro."
#endif

/*
 * The constants ROM_TEXT_ADRS, ROM_SIZE, RAM_HIGH_ADRS, and RAM_LOW_ADRS
 * are defined in config.h and Makefile.
 * All definitions for these constants must be identical.
 * The boot ROM is selectable with switch 8 on S4 on the 405EP eval board.
 * The jumper selects either a 512KB flash (Am29F040) OR 512KB of 8 bit SRAM.
 * If switch 8 is in the ON position the flash is selected.  If switch 8 is
 * in the OFF position the SRAM is selected. In order to write to the SRAM
 * with a JTAG debugger, be sure to first set EBC0_B0CR[BU] to '11'b because
 * after reset Bank 0 of the External Bus Controller defaults to "read-only".
 *
 * Boot ROM address space.
 */

#define ROM_BASE_ADRS         0xfff80000              /* base address of ROM  */
#define ROM_TEXT_ADRS         (ROM_BASE_ADRS + 0x100) /* with PC & SP         */
#define ROM_WARM_ADRS         (ROM_TEXT_ADRS+0x0004)  /* warm reboot entry    */
#define ROM_SIZE              0x00080000              /* 512KB                */
#define RAM_LOW_ADRS          0x00010000              /* RAM addr for vxWorks */
#define RAM_HIGH_ADRS         0x00c00000              /* RAM addr for bootrom */
#define USER_RESERVED_MEM     0                       /* see sysMemTop()      */

/*
    flash address space
*/

#define FLASH_BASE_ADRS1		0x02000000	
#define FLASH_SIZE1			0x00800000	/* 8M flash		*/


#define FLASH_BASE_ADRS2		0x02800000	
#define FLASH_SIZE2			0x00800000	/* 8M flash		*/


/*
 * Cache options
 */

#define INCLUDE_CACHE_SUPPORT

#define USER_D_CACHE_ENABLE
#define USER_I_CACHE_ENABLE
#undef  USER_D_CACHE_MODE
#define USER_D_CACHE_MODE       (CACHE_COPYBACK)


/*
 * Optional timestamp support
 */

#define INCLUDE_AUX_CLK
#undef  INCLUDE_TIMESTAMP

/*
 * Auxilliary Timer rates
 */

#define AUX_CLK_RATE_MIN     (sysTimerClkFreq / (1 << 21) )
#define AUX_CLK_RATE_MAX     (sysTimerClkFreq / (1 << 9)  )
#define AUX_CLK_RATE_DEFAULT (sysTimerClkFreq / (1 << 17) )

/*
 * Watchdog Timer rates
 */

#define WDT_RATE_MIN         (sysTimerClkFreq / (1 << 29) )
#define WDT_RATE_MAX         (sysTimerClkFreq / (1 << 17) )

/* Real Time Clock configuration */

#define INCLUDE_RTC

/* Remove unused network drivers */

#undef  INCLUDE_EI
#undef  INCLUDE_EX
#undef  INCLUDE_ENP
#undef  INCLUDE_LN
#undef  INCLUDE_SM_NET
#undef  INCLUDE_SM_SEQ_ADDR


/* #define for software floating point support */

#undef INCLUDE_SW_FP

/* Serial port configuration */

#define  INCLUDE_SIO


/* PCI configuration */

#undef INCLUDE_PCI

#ifdef INCLUDE_PCI

#    define INCLUDE_PCI_AUTOCONF


/*   PCI bus memory map                                       controlled by
 *
 *   0x00000000 - 0x1FFFFFFF    Reserved for VGA                 (PMM2)
 *   0x20000000 - 0x3FFFFFFF    405EP slave window               (PTM1)
 *   0x40000000 - 0x5FFFFFFF    PCI Mem with prefetch            (PMM0)
 *   0x60000000 - 0x7FFFFFFF    PCI Mem w/o  prefetch            (PMM1)
 *   0x80000000 - 0xFFFFFFFF    unused                             -
 *
 */

/*
 * Define a 512MB slave window that allows PCI masters to access local memory
 * of the 405EP.  This window will be setup with the PTM1 registers in the
 * bridge.
 */

#    define PCI_SLV_MEM_LOCAL      LOCAL_MEM_LOCAL_ADRS
#    define PCI_SLV_MEM_BUS        LOCAL_MEM_LOCAL_ADRS
#    define PCI_SLV_MEM_SIZE       0x80000000           /* 2GB */

#    define PTM1_LOCAL_ADRS        PCI_SLV_MEM_LOCAL
#    define PTM1_SIZE_ATTRIB       PTM_SIZE_2GB | PTM_ENABLE

/*
 * Define a 512MB master window that allows the CPU to access PCI Memory
 * (with prefetch).  This window will be setup with the PMM0 registers in the
 * bridge.
 */

#    define PCI_MSTR_MEM_LOCAL     PCI_MEMORY_START
#    define PCI_MSTR_MEM_BUS       PCI_MEMORY_START
#    define PCI_MSTR_MEM_SIZE      0x02000000           /* 32MB */

#    define PMM0_LOCAL_ADRS        PCI_MSTR_MEM_LOCAL
#    define PMM0_PCI_LOW_ADRS      PCI_MSTR_MEM_BUS
#    define PMM0_PCI_HIGH_ADRS     0x00000000
#    define PMM0_PCI_MASK_ATTRIB   (PMM_MASK_32MB | PMM_PREFETCH | PMM_ENABLE)

/*
 * Define a 32KB master window that allows the CPU to access PCI Memory
 * (non-prefetch). This window will be setup with the PMM1 registers in
 * the bridge.
 */

#    define PCI_MSTR_MEMIO_LOCAL   (PCI_MEMORY_START + PCI_MSTR_MEM_SIZE)
#    define PCI_MSTR_MEMIO_BUS     (PCI_MSTR_MEM_BUS + PCI_MSTR_MEM_SIZE)
#    define PCI_MSTR_MEMIO_SIZE    0x02000000           /* 32MB */

#    define PMM1_LOCAL_ADRS        PCI_MSTR_MEMIO_LOCAL
#    define PMM1_PCI_LOW_ADRS      PCI_MSTR_MEMIO_BUS
#    define PMM1_PCI_HIGH_ADRS     0x00000000
#    define PMM1_PCI_MASK_ATTRIB   (PMM_MASK_32MB | PMM_ENABLE)

/*
 * Master window that allows CPU to access PCI I/O space.
 */

#    define PCI_MSTR_IO_LOCAL      PLB_PCI_IO_REGION_1_START
#    define PCI_MSTR_IO_BUS        0x00000000
#    define PCI_MSTR_IO_SIZE       PLB_PCI_IO_REGION_1_SIZE

/*
 * The third PCI master memory window can be used to address VGA type devices
 * at PCI address 0x00000000.
 */

#    define PMM2_LOCAL_ADRS       (PCI_MSTR_MEMIO_LOCAL + PCI_MSTR_MEMIO_SIZE)
#    define PMM2_PCI_LOW_ADRS     0x00000000
#    define PMM2_PCI_HIGH_ADRS    0x00000000
#    define PMM2_PCI_MASK_ATTRIB  (PMM_MASK_32MB | PMM_ENABLE)

/*
 * The second PCI slave window in the in the bridge are not being used.
 */

#    define PTM2_LOCAL_ADRS       PTM_UNUSED
#    define PTM2_SIZE_ATTRIB      PTM_UNUSED

/* PCI Latency Timer value */
#    define PCI_LAT_TIMER          0     /* ZZZZZZZZZZZZZ */
#    define INCLUDE_SHOW_ROUTINES        /* ZZZZZZZZZZZZZ */

#endif /* INCLUDE_PCI */

/*
 * If network support is included, either the native EMAC or the PCI Ethernet
 * should be chosen. Both are END style drivers.
 */
#define INCLUDE_NETWORK
#define INCLUDE_EMAC_NETWORK             /* 405EP native EMAC network support */
#undef  INCLUDE_LN97XEND                 /* PCI network support               */


#ifdef INCLUDE_EMAC_NETWORK
#    undef   IP_MAX_UNITS
#    define  IP_MAX_UNITS  2
#endif

/*
 * WDB communication is via an Enhanced Network Driver
 */

#ifdef  INCLUDE_NETWORK
#  define INCLUDE_END
#  undef  WDB_COMM_TYPE
#  define WDB_COMM_TYPE        WDB_COMM_END
#endif  /* INCLUDE_NETWORK */

#define VEC_BASE	(char *)0

/*
 * MMU support.
 * By default only DMMU is enabled, and the IMMU is disabled for performance
 * reasons. This enable setting page level cacheability control for data
 * loads and stores, whereas the instruction cacheability is controlled by
 * ICCR. This reduces contention for the TLB entries by the IMMU and also
 * improves performance due to lesser TLB misses. If you want to enable
 * the IMMU, change the #undef below.
 */
#define  INCLUDE_MMU_BASIC
#define  USER_D_MMU_ENABLE
#undef   USER_I_MMU_ENABLE

#include "ibmEvb405EP.h"       /* board header file          */
#include "ppc405EP.h"          /* chip header file           */

/*
 * On the 405 CPU we cannot enable the MMU unless the caches are initialized
 * (unless ofcourse we mark the entire address space as un-cacheable). There
 * is no separate way of disabling the caches when the MMU is enabled, other
 * than on a page-by-page basis. Hence it is recommended that caches always
 * be used whenever the MMU is used.
 */
#ifdef INCLUDE_MMU_BASIC
    #ifndef INCLUDE_CACHE_SUPPORT
    #error "You need to include Cache support for MMU support."
    #endif
#endif

/* Include the other configuration values */

#endif  /* INCconfigh */
#if defined(PRJ_BUILD)
#include "prjParams.h"
#endif