target.nr

移植好的Ibm405ep bsp板极支持包

IBM PowerPC 405EP ibmEvb405EP target specific documentation
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.\" ibmEvb405EP/target.nr - IBM 405EP target specific documentation
.\"
.\" Copyright 1984-2000 Wind River Systems, Inc.
.\"
.\" modification history
.\" --------------------
.\" 01a,16jul02,mcg   created
.\"
.TH ibmEvb405EP T "IBM PPC405EP EVB" "Rev: 15 Dec 00" "TORNADO REFERENCE: VXWORKS"

.SH "NAME"
IBM PPC405EP EVB

.SH "INTRODUCTION"
This manual entry provides board-specific information necessary to run
VxWorks for the ibmEvb405EP (IBM PPC405EP) BSP. Before using a board with VxWorks,
verify that the board runs in the factory configuration by using
vendor-supplied ROMs and jumper settings and checking the RS-232
connection.

.SS "Boot ROMs"
The IBM 405EP Evaluation Board uses a single AMD Am29F040 ROM
(total 512KB).  Install the ROM as follows:

.TS
center;
cf3 cf3
a a .
ROM	Socket
_
\(mi	U18
.TE

The BSP uses the NVRAM on the Dallas Semiconductor DS1743.  Boot parameters
will be preserved here when the system is powered off.

To load VxWorks, and for more information, follow the instructions in the
.I "Tornado User's Guide: Getting Started."

.SS "Jumpers"
Jumpers J22 and J24 should both be installed so the Cypress C9531 Clock
Generator supplies a 33MHz clock to the 405EP.

.SS "Switch Settings"
The following switch settings apply:

\ts
Part | Switch | Setting | Description
-- | --- | ------- | ---------------------------------------------
S4 | SW1 | ON = 0  | Disable configuration SEEPROM
S4 | SW2 | ON = 0  | BootROM width 8 bit
S4 | SW3 | ON = 0  | BootRom width 8 bit
S4 | SW4 | ON = 0  | PCI frequency select (see board user manual)
S4 | SW5 | OFF = 1 | Use PCI internal arbiter
S4 | SW6 | ON = 0  | Use on board PCI clock
S4 | SW7 | ON = 0  | Use on board flash
S4 | SW8 | ON = 0  | Flash starts at 0xFFF80000, SRAM starts at 0xFFF00000
\te


.SH "FEATURES"

.SS "Supported Features"

The following features are supported in this release:
   - MMU on the PPC405EP processor (MMU_BASIC only).
   - System Timer (uses 405EP PIT hardware timer)
   - Auxiliary Timer (uses 405EP FIT hardware timer)
   - Watchdog Timer (uses 405EP WDT hardware timer)
   - Both 405EP 16550-style serial ports
   - 405EP Universal Interrupt Controller (UIC)
   - 405EP Memory Access Layer (MAL)
   - Both 405EP 10/100Mbps Ethernet intefaces (EMAC)
   - 405EP integrated PCI controller (PCI autoconfiguration)
   - AMD 79C97x family of Ethernet controller (using ln97xEnd driver)
      - Allied Telesyn 2450T  adapter (AMD 79C970) has been tested
      - Allied Telesyn 2700TX adapter (AMD 79C972) has been tested
      - other adapters with the same AMD controller may also work.
   - SDRAM autoconfiguration (the default SDRAM DIMM can be replaced with
     up to a 256MB DIMM) using the IIC interface to read the DIMM SEEPROM
   - NVRAM (Dallas Semiconductor DS1743)
   - Real-time clock (Dallas Semiconductor DS1743) using ds1643rtc.c driver
   - JTAG RISCWatch bootrom flash programming tool
   - 405EP DMA controller (memory-to-memory only)

.SS "Unsupported Features"
   - Use of the 405EP configuration SEEPROM.  Configuration parameters
     that can be set by the configuration SEEPROM are set by code instead.
   - 405EP on-chip memory (OCM)
   - 405EP event counters
   - 405EP general purpose timers
   - 405EP power management features

.SH "HARDWARE DETAILS"
This section documents the details of the device drivers and board
hardware elements.

.SS "Devices"
The chip drivers used by this BSP are:

    evbNs16550Sio.c - 16550 serial driver
    ppc405Timer.c - timer driver for the 405 processor core
    byteNvRam.c - generic non-volatile RAM driver
    uicIntr.c - on-chip Universal Interrupt controller

This bsp also provides the following chip drivers:

    d1643RTC.c - RTC DS1643 real time clock driver
    ibmDma.c - IBM DMA controller driver
	
It also provides DCR access routines for all DCR registers in the chip:
	sysDcrInLong()
        sysDcrOutLong()
	
.SS "Memory Maps"

This BSP supports MMU on the PPC405EP processor. Memory is mapped using a
fixed page size of 4K.

The sysPhysMemDesc[] array in sysLib.c is used to initialize the Page Table
Entry (PTE) array used by the MMU to translate addresses with single page
(4k) granularity. Address translations for local RAM, memory mapped PCI bus,
memory mapped IO space and local PROM/FLASH are set here. PTEs are held in a
2-level page table. There is one Level 1 page table and several Level 2 page
tables. The size of the Level 1 table is 4K and the size of each Level 2 page
table is 8K. Each Level 2 table can map upto 4MB of contiguous memory space.

.SS "Calculating size of page table required"

For the following memory map we can calculate the page table size
required as follows:

.TS
expand;
l l l l .
Memory Area	Address Range Mapped	Size	Number of Level 2 pages
-
Local Memory	0 - Ram size	32MB	8
PCI Memory	0x80000000-0x83FFFFFF	64MB	16
PCI IO Regn 1	0xE8000000-0xE800FFFF	64K	1
PCI IO Regn 2	0xE8800000-0xE88FFFFF	1MB	1
PCI CFG	0xEEC00000-0xEEC00FFF	4K	1
PCI IACK	0xEED00000-0xEED00FFF	4K	0 *
PP Bridge	0xEF400000-0xEF400FFF	4K	1
UART IO Space	0xEF600000-0xEF600FFF	4K	0 *
NVRAM Space	0xF0000000-0xF0001FFF	8K	1
FPGA Space	0xF0300000-0xF0300FFF	4K	1
Flash	0xFFF80000-0xFFFFFFFF	512K	1
.TE

	* included in previous L2 page

	Total # of L2 pages = 31
	Total Memory Required for page table = 31 * 8 + 4 = 252 K.

By default, to increase performance the instruction MMU (IMMU) is turned
off. In this case, instruction cacheability is controlled by ICCR (which
by default is set to cache all RAM). The IMMU can be re-enabled by defining
USER_I_MMU_ENABLE in config.h.

.SS "PCI"

The internal PCI arbiter of the 405EP has only 3 external REQ#/GNT# signal
pairs.  The three signal pairs are wired to 3 of the 4 PCI slots
(J36, J38, and J42). PCI slot J35 should therefore not be used if the internal
PCI arbiter is enabled.  The external PCI arbiter (located in the FPGA) supports
all four PCI slots.

.SS "Serial Configuration"
The default configuration of the serial ports are 9600bps, 8 data bits,
no parity, 1 stop bit.

.SS "Network Configuration"

The Enhanced Network Driver (END) used with the integrated EMAC Ethernet
core is "ibmEmacEnd": Note that the boot device name is now "emac", rather
than "ibmEmac". The EMAC works at either 10Mbps or 100Mbps.  EMAC
gets the results of the PHY's auto-negotiation process over the MII
interface.

Since MAL is a Processor Local Bus (PLB) master, its accesses to system
memory are unknown to the processor's L1 cache because there is no hardware
enforced cache coherency in the 405EP.  The ibmEmacEnd driver maintains
coherency for both buffer descriptors and buffers.


The following are not supported in the current driver:

		 - wake-on-LAN
		 - VLAN tagged frames


If desired, an AMD 79C97x PCI Ethernet card can be plugged into the
board.  This controller uses the ln97xEnd driver provided with Tornado 2.0.

The Ethernet hardware address is configurable at run-time.
The first three bytes of the address are always assumed to be 0x0004AC
(IBM) and the last three bytes are configurable and stored in NVRAM at
address 0xF0000500.  To make the ethernet hardware address match the address
printed on the decal attached to the board use the following example
as a guide.


Ethernet hardware address on the board decal:  0004AC3E4B22
	- boot VxWorks
	- execute the following command from the shell:

		sysLanIbmEmacEnetAddr0Set 0x00, 0x04, 0xAC, 0x3E, 0x4B, 0x22
		
To set the hardware address of EMAC1, the function sysLanIbmEmacEnetAddr1Set
should be used.

.SS "Supported BootRom builds"

*** Note:  Tornado bootrom builds are only supported through the command
line makefiles -- do not use the Tornado IDE to build a boot ROM.

The boot record must be added manually to the bootrom_uncmp.hex file.
Please add the following line to the file just prior to the
end-of-file (s9) record.

	 S20807FFFC4BF80102AF

The above record inserts an absolute branch from the 405EP reset vector
(0xFFFFFFFC) to the entry point of the VxWorks bootrom (0xFFF80100).
Disassembled, it looks like this:

	 Addr         Data         Disassembled
	 -----------------------------------------
	 0xFFFFFFFC   4BF80102     ba   0xFFF80100

.SS "Creating a bootrom, and bringing up vxWorks"

Create a bootrom by either

 a) Rebuilding a bootrom_uncmp.hex or bootrom.hex image and programming
    it into an AMD 29F040 flash part using the following steps:

	- make bootrom_uncmp.hex or bootrom.hex

	- Add the boot vector record to bootrom_uncmp.hex (see Supported
	  bootrom "builds" section above).  This step is not necessary if
	  you are using the vx_rw_flash.cmd to program the flash part on the
	  board.

 b) If you have a JTAG RISCWatch processor probe, you can use
    vx_rw_flash.cmd to program the flash part (see below).


Connect a terminal or terminal emulator to the board (the 9 pin connector
closest to the printed circuit board).  Emulator parameters should be set
to 9600bps, 8 data bits, no parity, 1 stop bit.
Power-up the board, you should get an error because the default boot
line in config.h is not 100% correct for your environment.  Type in new
configuration parameters using the bootrom menu
(set boot device : emac).
Your new configuration will be stored in the NVRAM.


.SS "RISCWatch bootrom flash programming utility"

An IBM RISCWatch based command file (vx_rw_flash.cmd) is provided that
will program bootrom_uncmp.hex into the AMD Am29F040 flash part on the
board. A RISCWatch JTAG processor probe and RISCWatch software
version 4.5 or newer is required to use this utility.

To use this utility,
  - make bootrom_uncmp.hex or bootrom.hex via the command line interface (not with the IDE).
	NOTE: The manual step of adding the branch instruction to
	bootrom_uncmp.hex or bootrom.hex is NOT necessary if using this utility!
  - Start IBM JTAG RISCWatch
  - Make sure that the RISCWatch search path is set up to find files
	in the BSP directory.  One way to do this is to execute the
	following RISCWatch command:
	   srchpath add c:\Tornado\target\config\ibmEvb405EP
  - Execute the following command to start the flash programming process.
	This example will place the bootrom_uncmp.hex file into the flash.
	   exec vx_rw_flash.cmd {"bootrom_uncmp.hex"}


.SH "SPECIAL CONSIDERATIONS"
.SS "Debugging with RISCWatch"
  To use RISCWatch with BSP code or VxWorks application code, the following
  compiler options are necessary to get the proper debug information into
  the executable.

         -gdwarf -O0

.SS "Known Problems"
- None at this time.

.SH "SEE ALSO"
.tG "Getting Started,"
.pG "Configuration,"
.pG "Architecture Appendix"

.SH "BIBLIOGRAPHY"
Please refer to the following documents for further information on the
IBM 405EP evaluation board.

.iB "PowerPC 405EP Reference Board Manual"
http://www-3.ibm.com/chips/techlib/techlib.nsf/productfamilies/PowerPC_Tools_and_Evaluation_Kits