ibmevb405ep.h

移植好的Ibm405ep bsp板极支持包

/* ibmEvb405EP.h - IBM 405EP eval board (Bubinga) header */

/*******************************************************************************
   This source and object code has been made available to you by IBM on an
   AS-IS basis.

   IT IS PROVIDED WITHOUT WARRANTY OF ANY KIND, INCLUDING THE WARRANTIES OF
   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE OR OF NONINFRINGEMENT
   OF THIRD PARTY RIGHTS.  IN NO EVENT SHALL IBM OR ITS LICENSORS BE LIABLE
   FOR INCIDENTAL, CONSEQUENTIAL OR PUNITIVE DAMAGES.  IBMS OR ITS LICENSORS
   DAMAGES FOR ANY CAUSE OF ACTION, WHETHER IN CONTRACT OR IN TORT, AT LAW OR
   AT EQUITY, SHALL BE LIMITED TO A MAXIMUM OF $1,000 PER LICENSE.  No license
   under IBM patents or patent applications is to be implied by the copyright
   license.

   Any user of this software should understand that neither IBM nor its
   licensors will be responsible for any consequences resulting from the use
   of this software.

   Any person who transfers this source code or any derivative work must
   include the IBM copyright notice, this paragraph, and the preceding two
   paragraphs in the transferred software.

   Any person who transfers this object code or any derivative work must
   include the IBM copyright notice in the transferred software.

   COPYRIGHT   I B M   CORPORATION 2000
   LICENSED MATERIAL  -  PROGRAM PROPERTY OF  I B M"

*******************************************************************************/

/* Copyright 1984-1999 Wind River Systems, Inc. */

/*
modification history
--------------------
01a,11may02,mcg  created ibmEvb405EP version from walnut version 01d
*/

/*
This file contains I/O addresses and related constants for the IBM
ibmEvb405EP BSP.  This board has the PowerPC 405EP embedded controller on it.
*/

#ifndef INCibmEvb405EPh
#define INCibmEvb405EPh

/* generic macros */

#ifndef EIEIO_SYNC
# define EIEIO_SYNC  __asm__(" eieio; sync")
#endif  /* EIEIO_SYNC */

#ifndef EIEIO
# define EIEIO  __asm__(" eieio")
#endif  /* EIEIO */

#ifndef SYNC
# define SYNC  __asm__(" sync")
#endif  /* SYNC */


#define BUS             NONE                 /* no off-board bus interface    */
#define N_SIO_CHANNELS  2                    /* Number of serial I/O channels */

/*
 * Minimum and maximum system clock rates
 */
#define SYS_CLK_RATE_MIN        3            /* minimum system clock rate     */
#define SYS_CLK_RATE_MAX        5000         /* maximum system clock rate     */

/*
 * Board clock frequencies
 */
#define ONE_BILLION        1000000000
#define C9531_INPUT_FREQ     33000000        /* 33.3 MHz to Cypress C9531     */


/*
 * Exception Vector Prefix Register value.  Exception vectors will be located
 * at the start of SDRAM.
 */

#define EVPR_VAL_405    0x00000000

/*
 * Initial values for UIC interrupt controller polarity, triggering, and
 * critical vs. non-critical.
 * All interrupts are postive-active except for PCI SERR and PCI slots (IRQ3-6).
 * All interrupts are level triggered except for the IRQ2 pushbutton switch.
 * All interurpts are non-critical except for the IRQ2 pushbutton switch.
 */

#define UIC0_INTR_POLARITY  0xFFFF7FF0
#define UIC0_INTR_TRIGGER   0x00000010
#define UIC0_INTR_CRITICAL  0x00000010

/*
 * PCI
 */

#ifdef INCLUDE_PCI
    /* Translate PCI addresses to virtual addresses (master windows) */

#ifndef PCI_MEM2LOCAL
#define PCI_MEM2LOCAL(x) \
        ((void *)((UINT)(x) - PCI_MSTR_MEM_BUS + PCI_MSTR_MEM_LOCAL))
#endif

#ifndef PCI_IO2LOCAL
#define PCI_IO2LOCAL(x) \
        ((void *)((UINT)(x) - PCI_MSTR_IO_BUS + PCI_MSTR_IO_LOCAL))
#endif

#ifndef PCI_MEMIO2LOCAL
#define PCI_MEMIO2LOCAL(x) \
        ((void *)((UINT)(x) - PCI_MSTR_MEMIO_BUS + PCI_MSTR_MEMIO_LOCAL))
#endif

    /* Translate local memory address to PCI address (slave window) */

#ifndef LOCAL2PCI_MEM
#define LOCAL2PCI_MEM(x) \
        ((void *)((UINT)(x) - PCI_SLV_MEM_LOCAL + PCI_SLV_MEM_BUS))
#endif

/*
 * Routines for reading or writing PCI I/O or Memory space. These routines are
 * written in assembler and use byte swapping load/store instructions.
 */

#ifndef PCI_IN_BYTE
#define PCI_IN_BYTE(x)         sysPciInByte (x)
#endif
#ifndef PCI_IN_WORD
#define PCI_IN_WORD(x)         sysPciInWord (x)
#endif
#ifndef PCI_IN_LONG
#define PCI_IN_LONG(x)         sysPciInLong (x)
#endif
#ifndef PCI_OUT_BYTE
#define PCI_OUT_BYTE(x,y)      sysPciOutByte (x,y)
#endif
#ifndef PCI_OUT_WORD
#define PCI_OUT_WORD(x,y)      sysPciOutWord (x,y)
#endif
#ifndef PCI_OUT_LONG
#define PCI_OUT_LONG(x,y)      sysPciOutLong (x,y)
#endif

#endif /* INCLUDE_PCI */

/*
 * The Allied Telesyn AT-2700TX card contains the AMD Am79C972 controller
 * (PCnet-FAST+).  Below is the information for the PCI vendor and device
 * IDs for the AMD Am79C97x family and registers where the MAC address can be
 * found after it is loaded from the serial EPROM on the PCI card.
 */
#ifdef INCLUDE_NETWORK
# ifdef INCLUDE_LN97XEND
#   define PCI_VENDOR_ID_AMD     0x1022
#   define PCI_DEVICE_ID_79C97X  0x2000

#   define APROM01               0           /* EEPROM registers */
#   define APROM23               2
#   define APROM45               4
#   define APROM_SIZE            16
# endif /* INCLUDE_LN97XEND */
#endif /* INCLUDE_NETWORK */

/*
 * Dallas Semiconductor DS1743P 8KB NVRAM with Real-Time Clock definitions
 * The first 1KB of the NVRAM is reserved for IBM Eval kit software use.
 * The last three bytes of the EMAC Ethernet hardware address are stored
 * after the boot information (offset 1KB + 256).  The first three bytes of
 * this address are assumed to be 0x0004ac.
 */

#define NV_RAM_ADRS     0xF0000000
#define NV_RAM_INTRVL   1
#define NV_RAM_SIZE     (8*1024) - 8            /* 8KB - 8 bytes for the RTC  */
#define NV_RAM_SIZE_ALIGNED     (8*1024)        /* page aligned size for MMU  */
#undef  NV_BOOT_OFFSET
#define NV_BOOT_OFFSET    0x400                 /* Offset of 1KB              */
#define NV_ENET_OFFSET_0  0x100                 /* Offset of Ethernet HW adrs */
                                                /* from the boot offset       */
#define NV_ENET_OFFSET_1  0x106                 /* Offset of Ethernet HW adrs */
                                                /* from the boot offset       */

#define RTC_BASE_ADRS   0xF0001FF8            /* real-time clock base address */


/*
 * The Ethernet hardware address that is used with EMAC is
 *
 *       0x0004ACnnnnnn
 *
 * where the first three bytes are defined below, and last three bytes are
 * stored in the NVRAM and can be modified by using the function
 * sysLanIbmEmacEnetAddrSet()
 */

#define ENET_DEFAULT            0x04AC00              /* IBM's fixed MAC addr */


/*
 * The address of the PHYs attached to the MII interfaces of the EMACs.
 */

#define EMAC_PHY_ADRS_0   1
#define EMAC_PHY_ADRS_1   2

/*
 * FPGA registers and bit definitions
 */

#define FPGA_BASE_ADRS       0xF0300000
#define FPGA_REG0            0xF0300000
#define FPGA_REG1            0xF0300001

/* FPGA register bits */

#define FPGA_REG0_F_RANGE     0x80       /* SDRAM PLL freq range              */
#define FPGA_REG0_EXT_INT_DIS 0x20       /* External interface disable        */
#define FPGA_REG0_EXT_IRQ     0x10       /*                                   */
#define FPGA_REG0_SMI         0x08       /*                                   */
#define FPGA_REG0_LED_MASK    0x07       /* Board LEDs DS9, DS10, and DS11    */
#define FPGA_REG0_LED0        0x04       /* Turn on LED0                      */
#define FPGA_REG0_LED1        0x02       /* Turn on LED1                      */
#define FPGA_REG0_LED2        0x01       /* Turn on LED2                      */

#define FPGA_REG1_SSPEC_DIS   0x80       /* C9531 Spread Spectrum disabled    */
#define FPGA_REG1_PCI_CLK_SEL 0x40       /* Onboard PCI clock selected        */
#define FPGA_REG1_CLOCK_MASK  0x30       /* Mask for C9531 output freq select */
#define FPGA_REG1_CLOCK_BIT_SHIFT  4
#define FPGA_REG1_PCI_INT_ARB 0x08       /* PCI Internal arbiter selected     */
#define FPGA_REG1_PCI_FREQ    0x04       /* PCI Frequency select              */
#define FPGA_REG1_OFFB_FLASH  0x02       /* Off board flash                   */
#define FPGA_REG1_SRAM_BOOT   0x01       /* SRAM at 0xFFF80000 not Flash      */



/*
 * There is 512KB of SRAM on the board.  It can reside in one of two
 * locations depending on the setting of switch 6 on bank U79.
 */
#define SRAM_START_ADRS  0xFFF00000
#define SRAM_SIZE        (512*1024)


/*
 * The 405EP eval board has one socket for a 168 pin SDRAM DIMM.
 * The following are offsets in the SDRAM DIMM's presence-detect serial EEPROM.
 * Values at these offsets are are accessed via the I2C interface, and
 * are used to help configure the SDRAM controller correctly for the
 * properties of the DIMM.
 */
#define SDRAM_NUM_ROWS     3
#define SDRAM_NUM_COLS     4
#define SDRAM_NUM_BANKS    5
#define SDRAM_WIDTH        6
#define SDRAM_NUM_INTBANKS 17
#define SDRAM_MOD_DENSITY  31

/*
 * The IIC addresses to read and write the Serial EEPROM on the SDRAM DIMM
 */
#define DIMM_READ_ADDR   0xAB
#define DIMM_WRITE_ADDR  0xAA

/*
 * External IRQ assignments, or how the UIC external interrupt pins
 * are actually used on the board.
 */
#define INT_VEC_PCI_SLOT3  INT_VEC_EXT_IRQ_3        /* J35 */
#define INT_VEC_PCI_SLOT2  INT_VEC_EXT_IRQ_4        /* J36 */
#define INT_VEC_PCI_SLOT1  INT_VEC_EXT_IRQ_5        /* J38 */
#define INT_VEC_PCI_SLOT0  INT_VEC_EXT_IRQ_6        /* J42 */

#define INT_LVL_PCI_SLOT3  INT_LVL_EXT_IRQ_3        /* J35 */
#define INT_LVL_PCI_SLOT2  INT_LVL_EXT_IRQ_4        /* J36 */
#define INT_LVL_PCI_SLOT1  INT_LVL_EXT_IRQ_5        /* J38 */
#define INT_LVL_PCI_SLOT0  INT_LVL_EXT_IRQ_6        /* J42 */



#ifndef _ASMLANGUAGE

/*
 * System information structure.  It is used to get information about the
 * 405EP PLL and operating frequencies.
 */

typedef struct
    {
    UINT32  pllCpuDiv;
    UINT32  pllPlbDiv;
    UINT32  pllOpbDiv;
    UINT32  pllExtBusDiv;
    UINT32  pllMalDiv;
    UINT32  pllPciDiv;
    UINT32  pllFwdADiv;
    UINT32  pllFwdBDiv;
    UINT32  pllFbkDiv;
    UINT32  freqInput;              /* input to 405EP, output of C9531 */
    UINT32  freqVCOMhz;             /* in MHz                          */
    UINT32  freqPLLOUTA;
    UINT32  freqProcessor;
    UINT32  freqPLB;
    UINT32  freqPCISync;            /* Internal Synchronous PCI clock */
    UINT32  freqPCI;
    UINT32  pciIntArbEn;            /* Internal PCI arbiter is enabled */
    } SYS_INFO;

#endif

#endif  /* INCibmEvb405EPh */