📄 rominit.s.bak
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..mode6: addi r4,0,0x5 b ..mode_set..mode5: addi r4,0,0x4 b ..mode_set..mode4: addi r4,0,0x3 b ..mode_set..mode3: addi r4,0,0x2 b ..mode_set..mode2: addi r4,0,0x1 b ..mode_set..mode1: addi r4,0,0x0..mode_set: /* * Determine the size of each bank by using the Module Bank Density * value stored in r7 as read from the SDRAM DIMM EEPROM. Since * the value currently in r7 contains the size per 64-bit * bank on the DIMM, we divide this value by 2 (shift right 1 bit) * to determine the size per 32-bit bank. */ srwi r7,r7,1 /* calc size per 32 bit bank */ cmpi 0,0,r7,0x02 /* check r7 for bank size */ beq ..meg8 /* and use value to calc bank end addr */ cmpi 0,0,r7,0x04 beq ..meg16 cmpi 0,0,r7,0x08 beq ..meg32 cmpi 0,0,r7,0x10 beq ..meg64 cmpi 0,0,r7,0x20 beq ..meg128 addi r7,0,0x100 /* must be 256M */ addi r15,0,0x6 /* set size bits (SDx_SZ) for MBxCF reg */ b ..set_mb..meg8: addi r7,0,0x08 addi r15,0,0x1 /* set size bits (SDx_SZ) for MBxCF reg */ b ..set_mb..meg16: addi r7,0,0x10 addi r15,0,0x2 /* set size bits (SDx_SZ) for MBxCF reg */ b ..set_mb..meg32: addi r7,0,0x20 addi r15,0,0x3 /* set size bits (SDx_SZ) for MBxCF reg */ b ..set_mb..meg64: addi r7,0,0x40 addi r15,0,0x4 /* set size bits (SDx_SZ) for MBxCF reg */ b ..set_mb..meg128: addi r7,0,0x80 addi r15,0,0x5 /* set size bits (SDx_SZ) for MBxCF reg */..set_mb: /* * Set the SDRAM memory configuration regs (MBxCF). To do this we must * first determine the number of 32-bit banks to be configured. Note * that the number of banks in r5 is the number of 64-bit banks as * read from the SDRAM DIMM EEPROM. Since the 405EP only supports * 32-bit memory, each 64-bit bank must be configured as 2 separate * 32-bit banks. We also use the address mode stored in r4, the * size per 32-bit bank stored in r7, and the bank size bits stored * in r15 to configure the SDRAM memory bank regsisters (MBxCF). * Note that Memory starts at address 0x00000000 and * continues contiguously. */ rlwinm r4,r4,13,0xFFFFFFFF /* set SDx_AM (addr mode field bits */ /* 16:18) to be used when setting */ /* MBxCF regs */ rlwinm r15,r15,17,0xFFFFFFFF /* set SDx_SZ (size field bits */ /* 12:14) to be used when setting */ /* MBxCF regs */ or r4,r4,r15 /* set SDx_AM & SDx_SZ fields - these */ /* settings are the same for all */ /* SDRAM banks since only 1 DIMM */ ori r4,r4,0x1 /* set SDx_BE bit (bank enable) */ rlwinm r7,r7,20,0xFFFFFFFF /* set r7 (size per bank) to be used */ /* for calculating the SDx_BA field */ /* (base addr field bits 0:9) */ /* when setting the MBxCF regs */ /* * Set SDRAM_B0CR for bank 0. No need to add r7 for bank 0 since base * address for SDRAM_B0CR is 0x00000000. */ addi r12,0,SDRAM_B0CR mtdcr SDRAM0_CFGADDR,r12 mtdcr SDRAM0_CFGDATA,r4 /* * Set SDRAM_B1CR for bank 1. Add r7 to get base address of this bank. */ addi r12,0,SDRAM_B1CR mtdcr SDRAM0_CFGADDR,r12 add r4,r4,r7 /* set base address for this bank */ /* by adding bank size to SDx_SZ field */ mtdcr SDRAM0_CFGDATA,r4..mb_set: /* * If SDRAM speed is 100MHz, use defaults for SDRAM Timing reg * (SDRAM_TR) and refresh timing register SDRAM_RTR. * * If SDRAM speed is 133MHz, set SDRAM Timing reg (SDRAM_TR) and * refresh rate register SDRAM_RTR accordingly. */#ifdef SDRAM_133 /* * Set SDRAM0_RTR value for 133MHz (7.5ns period). * Refresh rate approx = 15.24us/7.5ns = 2032 = 0x7F0. */ addis r3,r0,0x07F0 addi r12,0,SDRAM_RTR mtdcr SDRAM0_CFGADDR,r12 mtdcr SDRAM0_CFGDATA,r3 /* * Set SDRAM0_TR for 133MHz. Look at CAS latency value in R16 from * the SEEPROM to determine its proper setting in the TR register. */ cmpwi r16,0x75 /* compare to 7.5ns */ bgt ..cas13 addis r3,r0,0x008B /* CASL = 0x1, PTA=0x2, CTP=0x3 */ ori r3,r3,0x4016 /* LDF=0x1, RFTA=0x5, RCD=0x2 */ b ..set_tr..cas13: addis r3,r0,0x010B /* CASL = 0x2, PTA=0x2, CTP=0x3 */ ori r3,r3,0x4016 /* LDF=0x1, RFTA=0x5, RCD=0x2 */..set_tr: addi r12,0,SDRAM_TR mtdcr SDRAM0_CFGADDR,r12 mtdcr SDRAM0_CFGDATA,r3#endif /* CPU_SPEED_266 */ /* * Setup SDRAM_CFG regiter */ addis r9,0,0x8080 /* set value to program the SDRAM_CFG */ ori r9,r9,0x0000 /* reg; DC_EN=1, MEMCHK='00' to */ /* disable ECC, and BRD_PRF to '01' */ /* for 16 byte PLB burst read/prefetch */..cont1: cmpi 0,0,r10,0x16 /* Check DIMM MODEL ATTRIBUTES save in */ /* r10 to see if Registered memory; */ bne ..cont2 /* if registered (0x16) then */ addis r10,0,0x0800 /* update SDRAM_CFG reg value. Set */ or r9,r9,r10 /* R_DIMM_EN to enable registered mem */..cont2: /* * Delay to ensure 200usec have elapsed since reset. Assume worst * case that the core is running 200Mhz: * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ addis r3,0,0x0000 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ mtctr r3..spinlp2: bdnz ..spinlp2 /* spin loop */ /* * Set memory controller options reg, SDRAM_CFG with value in r9. * This enables the SDRAM controller. */ addi r12,0,SDRAM_CFG mtdcr SDRAM0_CFGADDR,r12 mtdcr SDRAM0_CFGDATA,r9 /* * Delay to ensure 10msec have elapsed since reset. This is * required for the MPC961 to stabilize. Assume worst * case that the core is running 200Mhz: * 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles * This delay should occur before accessing SDRAM. */ addis r3,0,0x001E ori r3,r3,0x8480 /* ensure 10msec have passed since reset */ mtctr r3..spinlp3: bdnz ..spinlp3 /* spin loop */#endif mtlr r31 blr#ifdef LOCAL_MEM_AUTOSIZE/********************************************************************************* iic0Init - Initializes the IIC0 for use during SDRAM* Automatic Configuration.* iic0Init* (* void* )*/iic0Init: /* * Initialize IIC0 controller. */ addis r3,0,HI(IIC0_BASE) /* base adrs of IIC0 cntlr */ ori r3,r3,LO(IIC0_BASE) addi r4,0,0x00 stb r4,IIC_LMADR(r3) /* clear lo master address */ eieio stb r4,IIC_HMADR(r3) /* clear hi master address */ eieio stb r4,IIC_LSADR(r3) /* clear lo slave address */ eieio stb r4,IIC_HSADR(r3) /* clear hi slave address */ eieio addi r4,0,0x08 stb r4,IIC_STS(r3) /* clear status */ eieio addi r4,0,0x8F stb r4,IIC_EXTSTS(r3) /* clear extended sattus */ eieio addi r4,0,0x03 /* set clock divisor */ stb r4,IIC_CLKDIV(r3) /* OPB 30-40Mhz => 3 */ eieio /* OPB 40-50Mhz => 4 */ addi r4,0,0x00 stb r4,IIC_INTRMSK(r3) /* no interrupts */ eieio stb r4,IIC_XFRCNT(r3) /* clear transfer count */ eieio addi r4,0,0xF0 stb r4,IIC_XTCNTLSS(r3) /* clear extended control & stat */ eieio addi r4,0,0x43 /* set mode control - flush */ stb r4,IIC_MDCNTL(r3) /* master data buf, enable hold */ eieio /* SCL, exit unknown state */ addi r4,0,0x00 stb r4,IIC_CNTL(r3) /* clear control reg */ eieio blr/********************************************************************************* iic0Read - Performs a one byte read from the SDRAM EEPROM on the* IIC0 bus.* UCHAE iic0Read* (* UCHAR byteNum* )*/ /* * iic0Read - does 1 byte read from SDRAM EEPROM on IIC0 bus. * iic combined format read requires a write of the byte we want to * read, before doing the read. */iic0Read: addis r10,0,HI(IIC0_BASE) /* r10 <-base addr of IIC0 cntlr */ ori r10,r10,LO(IIC0_BASE) addi r11,0,0x08 /* clear status */ stb r11,IIC_STS(r10) eieio addis r12,r0,0x0001 /* set up counter for timeout */ mtctr r12..chk_sts1: lbz r11,IIC_STS(r10) /* read status */ eieio andi. r11,r11,0x01 /* check for pending transfer */ beq ..sts_ok1 /* if 0, OK */ bdnz ..chk_sts1 /* * If we get here, we timed out on clear status */..iic0_timeout_fail_spin: b ..iic0_timeout_fail_spin /* halt - can not clear status */..sts_ok1: lbz r11,IIC_MDCNTL(r10) /* read mode control */ eieio ori r11,r11,0x40 /* flush master data buffer */ stb r11,IIC_MDCNTL(r10) eieio addi r11,0,DIMM_WRITE_ADDR /* set device address for */ stb r11,IIC_LMADR(r10) /* SDRAM EEPROM write (0xA0) */ eieio stb r3,IIC_MDBUF(r10) /* set device sub address */ /* which is the byte # to read */ addi r11,0,0x01 /* start write of 1 byte */ stb r11,IIC_CNTL(r10) eieio addis r12,r0,0x0001 /* set up counter for timeout */ mtctr r12..chk_sts2: lbz r11,IIC_STS(r10) /* read status */ eieio andi. r11,r11,0x01 /* check for pending transfer */ beq ..write_ok /* if 0, OK */ bdnz ..chk_sts2 /* * If we get here, we timed out on writing the SDRAM EEPROM * Could be No DIMM. Halt since memory can not be configured * properly without the EEPROM data. */..iic0Read_fail_spin: b ..iic0Read_fail_spin /* halt - read failed */..write_ok: addi r11,0,0x08 /* clear status */ stb r11,IIC_STS(r10) eieio addis r12,r0,0x0001 /* set up counter for timeout */ mtctr r12..chk_sts3: lbz r11,IIC_STS(r10) /* read status */ eieio andi. r11,r11,0x01 /* check for pending transfer */ beq ..sts_ok2 /* if 0, OK */ bdnz ..chk_sts3 /* * If we get here, we timed out on clear status */..iic0_timeout_fail_spin2: b ..iic0_timeout_fail_spin2 /* halt - can not clear status */..sts_ok2: lbz r11,IIC_MDCNTL(r10) /* read mode control */ eieio ori r11,r11,0x40 /* flush master data buffer */ stb r11,IIC_MDCNTL(r10) eieio addi r11,0,DIMM_READ_ADDR /* set device address for */ stb r11,IIC_LMADR(r10) /* SDRAM EEPROM (0xA1) */ eieio addi r11,0,0x03 /* read of 1 byte */ stb r11,IIC_CNTL(r10) eieio addis r12,r0,0x0001 /* set up counter for timeout */ mtctr r12..chk_sts4: lbz r11,IIC_STS(r10) /* read status */ eieio andi. r11,r11,0x01 /* check for pending transfer */ beq ..read_ok /* if 0, OK */ bdnz ..chk_sts4 /* * If we get here, we timed out on reading the SDRAM EEPROM * Could be No DIMM. Halt since memory can not be configured * properly without the EEPROM data. */..iic0Read_fail_spin2: b ..iic0Read_fail_spin2 /* halt - read failed */..read_ok: lbz r3,IIC_MDBUF(r10) /* read byte returned from EEPROM*/ eieio blr /* return with data in R3 */#endif /* LOCAL_MEM_AUTOSIZE */⌨️ 快捷键说明
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