📄 rominit.s.bak
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or r3, r8, r8 /* r3 = startType */ addi sp, sp, -FRAMEBASESZ /* get frame stack */ /* LOADPTR(r3,GPIO0_OR) /* Enable the output drivers */ /*lis r4,0x0000 /* For the GPIOs being used as outputs */ /* ori r4,r4,0x0000 stw r4,0(r3) */ blr /* branch to link register *//********************************************************************************* extBusCntlrInit - Initializes the 405EP External Bus Controller peripheral* bank registers for the board.** IMPORTANT: This code must run from the I-cache since the* peripheral bank timing register EBC_B0AP cannot be reliably* changed while code is being executed from bank 0.** Bank 0 - Flash/SRAM* Bank 1 - NVRAM/RTC* Bank 2 - not used* Bank 3 - not used* Bank 4 - FPGA registers* extBusCntlrInit* (* void* )*/extBusCntlrInit: mflr r4 /* save link register */ bl ..getAddr..getAddr: mflr r3 /* get address of ..getAddr */ mtlr r4 /* restore link register value */ addi r4,0,10 /* set ctr to 10; used to prefetch */ mtctr r4 /* 10 cache lines to fit this function */ /* in cache (8x10=80 instructions) */..ebcloop: icbt r0,r3 /* prefetch cache line for addr in r3 */ addi r3,r3,32 /* move to next cache line */ bdnz ..ebcloop /* continue for 10 cache lines */ /* * Delay to ensure all accesses to ROM are complete before changing * bank 0 timings. 200usec should be enough. * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ addis r3,0,0x0 ori r3,r3,0xA000 /* wait 200usec have passed since reset */ mtctr r3..spinlp: bdnz ..spinlp /* spin loop */ /* * Memory Bank 0 (Flash/SRAM) initialization */ addi r4,0,EBC_B0AP mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0400 ori r4,r4,0x6000 mtdcr EBC0_CFGDATA,r4 addi r4,0,EBC_B0CR mtdcr EBC0_CFGADDR,r4 addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */ ori r4,r4,0x8000 /* BW=0x0(8 bits) */ mtdcr EBC0_CFGDATA,r4 /* * Memory Bank 1 (NVRAM/RTC) initialization */ addi r4,0,EBC_B1AP mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0404 ori r4,r4,0x1000 mtdcr EBC0_CFGDATA,r4 addi r4,0,EBC_B1CR mtdcr EBC0_CFGADDR,r4 addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */ ori r4,r4,0x8000 /* BW=0x0(8 bits) */ mtdcr EBC0_CFGDATA,r4 /* * Memory Bank 2 (LCD interface) initialization */ #ifdef CPU_SPEED_266 addi r4,0,EBC_B2AP mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0702 ori r4,r4,0xa600 mtdcr EBC0_CFGDATA,r4 #endif #ifdef CPU_SPEED_200 addi r4,0,EBC_B2AP mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0a03 ori r4,r4,0xf600 mtdcr EBC0_CFGDATA,r4 #endif addi r4,0,EBC_B2CR mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0301 /*BAS=0x02c,BS=0x0(1MB),BU=0x3(r/w)*/ ori r4,r4,0x8000 /*BW=0x0(8 bits)*/ mtdcr EBC0_CFGDATA,r4 /* * Memory Bank 3 (flash 1) initialization */ addi r4,0,EBC_B3AP mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0400 ori r4,r4,0x6000 mtdcr EBC0_CFGDATA,r4 addi r4,0,EBC_B3CR mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0207 /* BAS=0x028,BS=0x1(2MB),BU=0x3(R/W), */ ori r4,r4,0x8000 /* BW=0x0(8 bits) */ mtdcr EBC0_CFGDATA,r4 /* * Memory Bank 4 (flash 2) initialization */ addi r4,0,EBC_B4AP mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0400 ori r4,r4,0x6000 mtdcr EBC0_CFGDATA,r4 addi r4,0,EBC_B4CR mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0287 /* BAS=0x02a,BS=0x1(2MB),BU=0x3(R/W), */ ori r4,r4,0x8000 /* BW=0x0(8 bits) */ mtdcr EBC0_CFGDATA,r4 blr/********************************************************************************* sdramInit - Initializes the 405EP SDRAM controller* Configures SDRAM memory banks.* Auto Memory Configuration option reads the SDRAM EEPROM* via the IIC bus and then configures the SDRAM memory* banks appropriately.* sdramInit* (* void* )*/sdramInit: mflr r31#ifndef LOCAL_MEM_AUTOSIZE /* * Fixed 32MB SDRAM configuration. */ /* * Set SDRAM_B0CR for bank 0. (0-16MB) Address Mode 4 */ addi r4,0,SDRAM_B0CR mtdcr SDRAM0_CFGADDR,r4 addis r4,0,0x0004 ori r4,r4,0x6001 mtdcr SDRAM0_CFGDATA,r4 /* * Set SDRAM_B2CR for bank 1. (16MB-32MB) Address Mode 4 */ addi r4,0,SDRAM_B1CR mtdcr SDRAM0_CFGADDR,r4 addis r4,0,0x0104 ori r4,r4,0x6001 mtdcr SDRAM0_CFGDATA,r4 /* * Take defaults for SDRAM Timing reg (SDRAM_TR) */ /* * Delay to ensure 200usec have elapsed since reset. Assume worst * case that the core is running 200Mhz: * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ addis r3,0,0x0000 ori r3,r3,0xff00 /* ensure 200usec have passed since reset */ mtctr r3..spinlp2: bdnz ..spinlp2 /* spin loop */ #ifdef SDRAM_133 /* * Set SDRAM0_RTR value for 133MHz (7.5ns period). * Refresh rate approx = 15.24us/7.5ns = 2032 = 0x7F0. */ addis r3,r0,0x07F0 addi r12,0,SDRAM_RTR mtdcr SDRAM0_CFGADDR,r12 mtdcr SDRAM0_CFGDATA,r3 /* * Set SDRAM0_TR for 133MHz. Look at CAS latency value in R16 from * the SEEPROM to determine its proper setting in the TR register. */ addis r3,r0,0x010B /* CASL = 0x2, PTA=0x2, CTP=0x3 */ ori r3,r3,0x4016 /* LDF=0x1, RFTA=0x5, RCD=0x2 */ addi r12,0,SDRAM_TR mtdcr SDRAM0_CFGADDR,r12 mtdcr SDRAM0_CFGDATA,r3#endif /* CPU_SPEED_266 */ /* * Set memory controller options reg, SDRAM_CFG. * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst * read/prefetch. */ addi r4,0,SDRAM_CFG mtdcr SDRAM0_CFGADDR,r4 addis r4,0,0x8080 /* set DC_EN=1 */ ori r4,r4,0000 mtdcr SDRAM0_CFGDATA,r4 /* * Delay to ensure 10msec have elapsed since reset. This is * required for the MPC961 to stabilize. Assume worst * case that the core is running 200Mhz: * 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles * This delay should occur before accessing SDRAM. */ addis r3,0,0x0028 ori r3,r3,0x96a0 /* ensure 10msec have passed since reset */ mtctr r3..spinlp3: bdnz ..spinlp3 /* spin loop */#else /* * Memory Auto Configuration. Reads EEPROM on the SDRAM DIMM via IIC * and sets the SDRAM controller appropriately. */ /* * Read bytes of interest on SDRAM EEPROM via iic_read subroutine. * These values are required to configure the SDRAM controller * properly. Data is stored in regs 4, 5, 6, 7, 16, and 10. */ addi r4,0,0x00 addi r5,0,0x00 addi r3,0,3 /* set byte to read (# ROWS) */ bl iic0Read ori r4,r3,0x00 /* store value in R4 */ addi r3,0,4 /* set byte to read (# COLS) */ bl iic0Read rlwinm r4,r4,8,0,31 /* make room for byte */ or r4,r3,r4 /* store value in R4 */ addi r3,0,17 /* set byte to read(# INT BANKS */ bl iic0Read rlwinm r4,r4,8,0,31 /* make room for byte */ or r4,r3,r4 /* store value in R4 */ addi r3,0,5 /* set byte to read (# BANKS) */ bl iic0Read ori r5,r3,0x00 /* store value in R5 */ addi r3,0,6 /* set byte to read (DATA WIDTH)*/ bl iic0Read ori r6,r3,0x00 /* store value in R6 */ addi r3,0,31 /* set byte to read (BANK SIZE) */ bl iic0Read ori r7,r3,0x00 /* store value in R7 */ addi r3,0,23 /* set byte to read (CASL) */ bl iic0Read ori r16,r3,0x00 /* store value in R16 */ addi r3,0,21 /* set byte to read (MODULE */ bl iic0Read /* ATTRIBUTES) */ ori r10,r3,0x00 /* store value in R10 */ /* * Force the data width to 64 bits. This will allow the 405EP to * treat an ECC DIMM as a non-ECC DIMM. 405EP does not support ECC. */ addi r6,0,0x40 /* * Now we have all the data from the SDRAM EEPROM needed in regs 4, 5 * 6 and 7. Reg 4 has # rows, # cols, and # internal banks in 3 LSBytes. * Reg 5 has # banks, Reg 6 has data width, and Reg 7 bank size. No more * iic reads are needed. Now the memory controller needs to be set * up properly based on the data from the SDRAM EEPROM. */ /* * Check r4 values to determine mode. Mode is determined by the * # rows, # cols, and # of internal banks. All three of these * parameters are stored in r4. Mode should be set as follows: * rows x cols (internal banks) * mode 1 - 11x9(2), 11X10(2) * mode 2 - 12x9(4), 12x10(4) * mode 3 - 13x9(4), 13x10(4), 13x11(4) * mode 4 - 12x8(2), 12x8(4) * mode 5 - 11x8(2), 11x8(4) * mode 6 - 13x8(2), 13x8(4) * mode 7 - 13x9(2), 13x10(2) * The mode must be programmed in each of the Memory Configuration * regs (MBxCF) for each enabled bank of SDRAM. Since we only have * one DIMM on the board, the mode will be the same for * each enabled SDRAM bank. */ addis r14,0,0x0B ori r14,r14,0x0902 cmp 0,0,r4,r14 /* 11x9(2) */ beq ..mode1 addis r14,0,0x0B ori r14,r14,0x0A02 cmp 0,0,r4,r14 /* 11x10(2) */ beq ..mode1 addis r14,0,0x0C ori r14,r14,0x0904 cmp 0,0,r4,r14 /* 12x9(4) */ beq ..mode2 addis r14,0,0x0C ori r14,r14,0x0A04 cmp 0,0,r4,r14 /* 12x10(4) */ beq ..mode2 addis r14,0,0x0D ori r14,r14,0x0904 cmp 0,0,r4,r14 /* 13x9(4) */ beq ..mode3 addis r14,0,0x0D ori r14,r14,0x0A04 cmp 0,0,r4,r14 /* 13x10(4) */ beq ..mode3 addis r14,0,0x0D ori r14,r14,0x0B04 cmp 0,0,r4,r14 /* 13x11(4) */ beq ..mode3 addis r14,0,0x0C ori r14,r14,0x0804 cmp 0,0,r4,r14 /* 12x8(4) */ beq ..mode4 addis r14,0,0x0C ori r14,r14,0x0802 cmp 0,0,r4,r14 /* 12x8(2) */ beq ..mode4 addis r14,0,0x0B ori r14,r14,0x0802 cmp 0,0,r4,r14 /* 11x8(2) */ beq ..mode5 addis r14,0,0x0B ori r14,r14,0x0804 cmp 0,0,r4,r14 /* 11x8(4) */ beq ..mode5 addis r14,0,0x0D ori r14,r14,0x0802 cmp 0,0,r4,r14 /* 13x8(2) */ beq ..mode6 addis r14,0,0x0D ori r14,r14,0x0804 cmp 0,0,r4,r14 /* 13x8(4) */ beq ..mode6 addis r14,0,0x0D ori r14,r14,0x0902 cmp 0,0,r4,r14 /* 13x9(2) */ beq ..mode7 addis r14,0,0x0D ori r14,r14,0x0A02 cmp 0,0,r4,r14 /* 13x10(2) */ beq ..mode7 /* * If we get here, then mode bytes read are invalid. * r4 contains the byte read. */..invalid_dimm_mode_spin: b ..invalid_dimm_mode_spin /* halt - invalid dimm mode */ /* * Store mode bit values in r4. We will use this value when * setting the SDx_AM field (bits 16:18 of the MBxCF regs) * for each of the SDRAM banks. */..mode7: addi r4,0,0x6 b ..mode_set⌨️ 快捷键说明
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