rominit.s.bak

移植好的Ibm405ep bsp板极支持包

/* romInit.s - IBM ibmEvb405EP ROM initialization module */

/*******************************************************************************
   This source and object code has been made available to you by IBM on an
   AS-IS basis.

   IT IS PROVIDED WITHOUT WARRANTY OF ANY KIND, INCLUDING THE WARRANTIES OF
   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE OR OF NONINFRINGEMENT
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   license.

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   licensors will be responsible for any consequences resulting from the use
   of this software.

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   include the IBM copyright notice, this paragraph, and the preceding two
   paragraphs in the transferred software.

   Any person who transfers this object code or any derivative work must
   include the IBM copyright notice in the transferred software.

   COPYRIGHT   I B M   CORPORATION 2000
   LICENSED MATERIAL  -  PROGRAM PROPERTY OF  I B M"

*******************************************************************************/

/* Copyright 1984-1998 Wind River Systems, Inc. */
        .data

/*
modification history
--------------------

01a,23may02,mcg  created from walnut romInit.s.
*/

/*
DESCRIPTION
This module contains the entry code for the VxWorks bootrom.
The entry point romInit, is the first code executed on power-up.
It sets the BOOT_COLD parameter to be passed to the generic
romStart() routine.

The routine sysToMonitor() jumps to the location 4 bytes
past the beginning of romInit, to perform a "warm boot".
This entry point allows a parameter to be passed to romStart().

*/

#define _ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "asm.h"
#include "config.h"
#include "regs.h"


        /* internals */

        .globl  romInit         /* start of system code */
        .globl  _romInit        /* start of system code */

        /* externals */

        .extern romStart        /* system initialization routine */

        .text
        .align 2
      
/*******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*

* romInit
*     (
*     int startType     /@ only used by 2nd entry point @/
*     )

*/

romInit:
_romInit:
        bl      cold
        bl      warm

        /* copyright notice appears at beginning of ROM (in TEXT segment) */

        .ascii   "Copyright 1984-1996 Wind River Systems, Inc."
        .align 4

cold:
        li      r8, BOOT_COLD
        bl      start                   /* skip over next instruction */

warm:
        or      r8, r3, r3              /* startType to r8 */

start:
        /*
         * Disable external interrupts by turning off CE and EE bits in MSR
         * Also turn off Machine Check until its vector is set up.
         */

        mfmsr   r3                      /* r3 = msr              */
        INT_MASK (r3, r4)               /* mask EE and CE bit    */
	rlwinm	r4, r4, 0, 20, 18	/* turn off _PPC_MSR_ME  */
        mtmsr   r4                      /* msr = r4              */
        isync

        /*
         * Initalize registers that need to be set to zero.
         */

        addi    r4,r0,0x0000
        mtspr   ICCR,r4                 /* turn off I-cache (warm)       */
        mtspr   DCCR,r4                 /* turn off D-cache (warm)       */
        mtspr   DCWR,r4                 /* all memory regions write-back */
        mtspr   ESR, r4                 /* clear error status            */
        mtspr   TCR, r4                 /* disable all timers            */
        mtspr   PIT, r4                 /* clear the PIT timer           */
        mtdcr   UIC0_ER, r4             /* disable ints at the UIC       */
        mtspr   XER, r4                 /* clear integer exception reg   */
        mtdcr   DMA0_CR0, r4            /* stop DMA channels             */
        mtdcr   DMA0_CR1, r4
        mtdcr   DMA0_CR2, r4
        mtdcr   DMA0_CR3, r4

        /*
         * Initalize registers that need to be cleared with 0xFFFFFFFF
         */

        addis   r4,r0,0xffff
        ori     r4,r4,0xffff
        mtspr   TSR, r4                 /* clear timer status            */
        mtspr   DBSR, r4                /* clear debug status reg        */
        mtdcr   DMA0_SR, r4             /* clear DMA status reg          */
        mtdcr   UIC0_SR, r4             /* clear all pending UIC ints    */

        /*
         * Set storage guarded attribute
         *     Unguarded: 0x00000000 - 0x7FFFFFFF  SDRAM
         *       Guarded: 0x80000000 - 0xF7FFFFFF  PCI Memory, I/O, config,
         *                                         405EP internal peripherals,
         *                                         external peripherals
         *     Unguarded: 0xF8000000 - 0xFFFFFFFF  Bootrom
         */

        addi    r4,r0,0x0000
        ori     r4,r4,0xfffe
        mtspr   SGR,r4

        /*
         * Invalidate the entire instruction cache. This can be done
         * with a single iccci instruction in the 405 processor core.
         */

        iccci   r0, r0

        /*
         * Invalidate the entire data cache.
         * The 405 processor core in the 405EP has 256 congruence classes.
         * Each cache line in the 405 processor is 32 bytes.
         */

        li      r3, 0                         /* clear r3 */
        li      r4, _DCACHE_LINE_NUM_405EP    /* load number of cache lines */
        mtctr   r4

rom403Dcci:
        dccci   r0, r3
        addi    r3, r3, _CACHE_ALIGN_SIZE       /* bump to next line */
        bdnz    rom403Dcci                      /* go to invalidate */


        /*
         * Check to see if the PLL is in bypass mode.
         * If so, write pre-determined values to CPC0_PLLMR0 and CPC0_PLLMR1
         * and perform a CPU reset.
         * If not in bypass mode, skip this step and keep going.
         * Note:  Running in bypass mode is not supported since PLB speed
         *        will not be fast enough for SDRAM (min 66MHz)
         */

        mfdcr   r5, CPC0_PLLMR1
        rlwinm  r4,r5,1,31,31            /* get system clock source (SSCS)*/
        cmpi    cr0,0,r4,0x1
        beq  pll_done                     /* PLL has already been set */
                                          /* skip to the next section */

        /*
         * Write pre-determined PLL and clock control settings into
         * CPC0_PLLMR0 and CPC0_PLLMR1.  See ibmEvb405EP.h.
         */
        lis     r3,HIADJ(PLLMR0_SETTING)
        addi    r3,r3,LO(PLLMR0_SETTING)
        mtdcr   CPC0_PLLMR0,r3            /* Set CPU/PLB/OPB/EBC dividers    */
        lis     r3,HIADJ(PLLMR1_SETTING)
        addi    r3,r3,LO(PLLMR1_SETTING)
        mtdcr   CPC0_PLLMR1,r3            /* Set PLL multiplier and dividers */

        /*
         * Instead of using the SYSPLL lock bit in CPC0_BOOT,
         * just wait a minimum of 100us for the PLL to lock.
         * (See PLL section of the CMOS 27E databook).
         * At 266MHz, a spin loop of 26666 instructions should be more
         * than enough.
         */
        li      r3,26666
        mtctr   r3
pll_wait:
        bdnz    pll_wait

        /*
         * Finally, perform a 405 core reset.  This will cause the 405 to
         * start executing instructions from the power-on vector
         * of 0xfffffffc.  When the PLL bypass check above is done again,
         * the PLL won't be in bypass mode and the setup should be skipped.
         */
        lis     r3,0x1000
        mtspr   DBCR0,r3


pll_done:

        /*
         * Turn the instruction cache on for faster boot-up.
         * Also, the icache is needed to help initialize Bank 0
         * of the EBC to speed up accesses to flash.
         * address space 0x00000000-0x07ffffff is cached
         * address space 0xf8000000-0xffffffff is cached
         */

        lis     r3, HIADJ(_PPC405_ICCR_DEFAULT_VAL)
        addi    r3, r3, LO(_PPC405_ICCR_DEFAULT_VAL)
        mtspr   ICCR, r3
        isync

        /*
         * Initialize GPIO pins.  Configure for instruction trace, external
         * interrupts, UARTs.
         *
         *  GPIO [0]     - External Bus Controller BLAST output
         *  GPIO [1-9]   - Instruction trace outputs
         *  GPIO [10-13] - External Bus Controller CS_1 - CS_4 outputs
         *  GPIO [14-16] - External Bus Controller ABUS3-ABUS5 outputs
         *  GPIO [17-23] - External Interrupts IRQ0-IRQ6 inputs
         *  GPIO [24-27] - UART0 control signal inputs/outputs
         *  GPIO [28-29] - UART1 data signal input/output
         *  GPIO [30-31] - EMAC0 and EMAC1 reject packet inputs
         */
     /*   LOADPTR(r3,GPIO0_OR)     /* Enable the output drivers           */
     /*  lis     r4,0xffff          /* For the GPIOs being used as outputs */
      /*  ori     r4,r4,0xffff
        stw     r4,0(r3)*/
        
        LOADPTR(r3,GPIO0_OSRH)     /* output select */
        lis     r4,0x4015
        ori     r4,r4,0x5555
        stw     r4,0(r3)

        LOADPTR(r3,GPIO0_OSRL)
        lis     r4,0x4000
        ori     r4,r4,0x0010
        stw     r4,0(r3)

        LOADPTR(r3,GPIO0_ISR1H)    /* input select */
        lis     r4,0x0000
        ori     r4,r4,0x0000
        stw     r4,0(r3)

        LOADPTR(r3,GPIO0_ISR1L)
        lis     r4,0x1555
        ori     r4,r4,0x5445
        stw     r4,0(r3)

        LOADPTR(r3,GPIO0_TSRH)     /* three-state select */
        lis     r4,0x0000
        ori     r4,r4,0x0000
        stw     r4,0(r3)

        LOADPTR(r3,GPIO0_TSRL)
        lis     r4,0x0000
        ori     r4,r4,0x0000
        stw     r4,0(r3)

        LOADPTR(r3,GPIO0_TCR)      /* Enable the output drivers           */
        lis     r4,0xFFFF          /* For the GPIOs being used as outputs */
        ori     r4,r4,0xff14
        stw     r4,0(r3)
        
        
        
 
        /*
         * Initialize External Bus Controller (EBC) for external peripherals
         */

        bl      extBusCntlrInit

        /*
         * Now that the EBC Bank 0 has been set up, turn the I-cache off if
         * i-cache was not specified in config.h.  It is also invalidated
         * again.
         */

#ifndef USER_I_CACHE_ENABLE
        li      r3, 0                     /* clear r3 */
        mtspr   ICCR, r3                  /* turn off i-cache */
        isync
        iccci   r0, r0                    /* invalidate the I-cache again */
#endif

        /*
         * Initialize IIC0 for use in automatic SDRAM configuration
         */

#ifdef LOCAL_MEM_AUTOSIZE
        bl      iic0Init
#endif

        /*
         * Configure the SDRAM controller only if this is a cold boot.
         * If the SDRAM controller is reinitialized on a warm boot, the
         * boot line will get wiped out because of the ECC SDRAM memory
         * initialization.
         */

        li      r3, BOOT_COLD
        and.    r3, r3, r8             /* r8 is saved at the entry of romInit */
        beq     skip

        bl      sdramInit

#ifdef INCLUDE_PCI

        /*
         * Determine from the FPGA register which PCI arbiter to use.
         * If internal, set the internal arbiter enable bit in CPC0_PCI.
         * This is done only on a cold boot because the PCI bridge must still
         * be held in reset.
         */

      /*  LOADPTR(r3,FPGA_REG1)                      /* Read FPGA_REG1 ,change by lp ,2004.10.18*/
      /*  lbz     r3,0x0(r3)*/
      /*  andi.   r3,r3,FPGA_REG1_PCI_INT_ARB*/
      /*  beq     relPci*/
      
        mfdcr   r3,CPC0_PCI
        ori     r3,r3,PCI_ARB_EN
        mtdcr   CPC0_PCI, r3

        /*
         * Now that the arbiter bit in CPC0_PCI is in the correct state,
         * release the PCI bridge from soft reset.  On a cold boot, the PCI bit
         * should be the only bit set in CPC0_SRR.
         */
relPci:
        xor     r3,r3,r3
        mtdcr   CPC0_SRR, r3

#endif   /* INCLUDE_PCI */

skip:

        /*
         * Clear the CPU reservation bit
         */

        li      r0, 0
        lwarx   r3, r0, r0
        stwcx.  r3, r0, r0

        /* Initialize the stack pointer (r1) */

        lis     sp, HIADJ(STACK_ADRS)
        addi    sp, sp, LO(STACK_ADRS)

#if     FALSE                           /* SDA not supported  */
        /* initialize r2 and r13 according to EABI standard */

        lis     r2, HIADJ(_SDA2_BASE_)
        addi    r2, r2, LO(_SDA2_BASE_)
        lis     r13, HIADJ(_SDA_BASE_)
        addi    r13, r13, LO(_SDA_BASE_)
#endif

        /* calculate C entry point: routine - entry point + ROM base */

        lis     r4, HIADJ(romStart)     /* r4 = romstart */
        addi    r4, r4, LO(romStart)

        lis     r5, HIADJ(romInit)      /* r5 = romInit */
        addi    r5, r5, LO(romInit)

        lis     r6, HIADJ(ROM_TEXT_ADRS) /* r6 = ROM_TEXT_ADRS */
        addi    r6, r6, LO(ROM_TEXT_ADRS)

        subf    r4, r5, r4              /* r4 = r4 - r5 */
        add     r4, r4, r6              /* r4 = r4 + r6 */
        mtlr    r4                      /* link register = C entry point */