initbrd.s
来自「Ibmstb02500 miniboot 源码」· S 代码 · 共 389 行
S
389 行
// openbios/arch/pallas/redwood5/initbrd.s, stbbios//------------------------------------------------------------------------------+//// This source code has been made available to you by IBM on an AS-IS// basis. Anyone receiving this source is licensed under IBM// copyrights to use it in any way he or she deems fit, including// copying it, modifying it, compiling it, and redistributing it either// with or without modifications. No license under IBM patents or// patent applications is to be implied by the copyright license.//// Any user of this software should understand that IBM cannot provide// technical support for this software and will not be responsible for// any consequences resulting from the use of this software.//// Any person who transfers this source code or any derivative work// must include the IBM copyright notice, this paragraph, and the// preceding two paragraphs in the transferred software.//// COPYRIGHT I B M CORPORATION 1995// LICENSED MATERIAL - PROGRAM PROPERTY OF I B M//-------------------------------------------------------------------------------//// File Name: initbrd.s//// Function: This is the architecture dependent init code for the ROM Monitor// shipped with the IBM REDWOOD5 / STB04xxx (Pallas).//// Author: Bill DeStein (initially)//// Change Activity-//// Date Description of Change BY// --------- --------------------- ---// 18-Mar-98 Ported to Redwood from Hawthorne pag// 25-Mar-98 bumped level for dccr fix pag// 26-Mar-98 bumped level for initializing sdram pag// 09-Apr-98 Fixed interrupt handling problem pag// 14-Jan-99 Porting to Redwood III pag// 31-Mar-99 Fixed code bug in data_ramc using r0 to move r3->r4 pag// 02-Apr-99 Changed code to support RIT-B & RIT-A (serial clock) pag// 02-Feb-00 Ported to Redwood IV Vesta STB jfh// 30-Dec-01 Splitted to architecture depdendent part from entry.s YYD// 21-Oct-03. Change xilinx reg 1 to enable Demux CI1 REL////-------------------------------------------------------------------------------// Tristate for other masters, diable ready time outs// xor r0, r0, r0 oris r1, r0,0x8000 mtdcr BIUCR, r1#ifdef PALLAS_PBA// Pallas 1 bug mfspr r6,pvr addis r7,r0,0x4181 ori r7,r7,0x0890 // Pallas 1 cmplw r6,r7 beq ctl_pass2 //----------------------------------------------------------------------- // Set up default chip interconnect //----------------------------------------------------------------------- /* Disable instruction unit pipelining */ /* Reduce Memory Request Priority from ICU */#endif#if 0 lis r3,0xB94B ori r3,r3,0xEDEE mtdcr cic0_sccr,r3#endif#ifdef PALLAS_PBA b ctl_pass1ctl_pass2: // Pallas 1 mfdcr r3,icbs0_cntl16 oris r3,r3,0x0020 mtdcr icbs0_cntl16,r3 mfspr r3,ccr0 lis r3,0x0000 ori r3,r3,0x0080 mtspr ccr0,r3ctl_pass1:#endif li r3,0x1000 mtdcr icbs0_config0,r3 oris r3,r3,0x1000 mtdcr icbs0_config1,r3 lis r3,0x8020 ori r3,r3,0x1000 mtdcr epi0_cr,r3 /* * Set up default chip interconnect */ addis r0,0,0x1B00 /* smartcd 1 interface is open drain */ mtdcr cic0_muxod,r0 addis r0,r0,0x1080 ori r0,r0,0x00E8 mtdcr cic0_cr,r0 addi r0,r0,0x0000 mtdcr cic0_sel3,r0 addis r0,r0,0x0043 ori r0,r0,0x1700 mtdcr cic0_vcr,r0// Initialize Bank 0 for 16 bit Flash// xor r0, r0, r0 // mtdcr brh0, r0 // Set Bus Region Config Hi reg 0 addis r1, 0, 0x0001 ori r1, r1, 0x8000 mfdcr r0, br0 // Get current bank reg 0 settings and r0, r0, r1 // Leave on only the bus width bits oris r0, r0,0xFC58 // 4 MB of flash ori r0, r0,0x3FFE // mtdcr br0, r0 // Set Bus Region Config reg 0//// Initialize Bank 2 for Xilinx// addis r0, r0, 0x4000 mtdcr brh2, r0 // Set Bus Region Config Hi reg 7 addis r0, r0,0x207C // ori r0, r0,0xD0BE // (with ready enabled) mtdcr br2, r0 // Set Bus Region Config reg 7//// Disable unused banks.// addis r6, r0,0xFF00 ori r6, r6,0xBFFF xor r0, r0, r0 // mtdcr brh3, r0 mtdcr br3, r6 mtdcr brh4, r0 mtdcr br4, r6 mtdcr brh5, r0 mtdcr br5, r6 mtdcr brh6, r0 mtdcr br6, r6 mtdcr brh7, r0 mtdcr br7, r6 //----------------------------------------------------------------------- // Invalidate i-cache and d-cache TAG arrays. //----------------------------------------------------------------------- addi r7, r0,256 // set r7 to # of lines in data cache // for loop count- romeo has 64 lines..dcache: addi r6,0,0x0000 // clear GPR 6 mtctr r7 // set loop ctr..dcloop: dccci 0, r6 // invalidate line addi r6, r6,0x20 // bump to next line bdnz ..dcloop..icache: addi r6,0,0x0000 // clear GPR 6..icloop: iccci 0, r6 // invalidates all i-cache// Cache Enable addis r1, r0,0x8000 addi r1, r1,0x0001 mticcr r1 //----------------------------------------------------------------------- // Initialize GPIOs to minimum options needed for OpenBIOS //----------------------------------------------------------------------- addis r4,r0,0x4006 // GPIO 0 addi r0,r0,0x0 stw r0,0x0000(r4) stw r0,0x0004(r4) addis r0,r0,0x5004 ori r0,r0,0x4101 stw r0,0x0008(r4) addis r0,r0,0xC540 ori r0,r0,0x2000 stw r0,0x000c(r4) addis r0,r0,0x5004 ori r0,r0,0x4104 stw r0,0x0010(r4) addis r0,r0,0xC540 ori r0,r0,0x2000 stw r0,0x0014(r4) addis r0,r0,0xC000 ori r0,r0,0x0040 stw r0,0x0018(r4) addis r0,r0,0x5001 ori r0,r0,0x0054 stw r0,0x0030(r4) addis r0,r0,0x0540 ori r0,r0,0x0000 stw r0,0x0034(r4) addis r0,r0,0x0000 ori r0,r0,0x0000 stw r0,0x0038(r4) addis r0,r0,0x0000 ori r0,r0,0x0000 stw r0,0x003C(r4) addis r0,r0,0x0400 ori r0,r0,0x1400 stw r0,0x0040(r4) addis r0,r0,0x1000 ori r0,r0,0x0000 stw r0,0x0044(r4) //----------------------------------------------------------------------- // Configure Minimal Xilinx needed for OpenBIOS to work //----------------------------------------------------------------------- addis r3,r0,0x7204 // Mux base address addi r0,r0,0x0119 sth r0,0x0(r3) addi r0,r0,0x0E0A sth r0,0x2(r3) addi r0,r0,0x06C9 sth r0,0x6(r3) addi r0,r0,0x0058 sth r0,0x8(r3) // Update Xilinx mux reg 5 addi r0,r0,0x60D1 sth r0,0xa(r3) // Update Xilinx mux reg 6 addi r0,r0,0x0008 sth r0,0xe(r3) // Clock all Xilinx mux regs /*-------------------------------------------------------------------------+ | CONFIGURE THE HSMC CONTROLLERS | Double map HSMC into 0x00000000/0x80000000 0x20000000/0xA0000000 +-------------------------------------------------------------------------*/ /* * */ li r1, 0x0a00 mtdcr sdram0_config,r1 mtdcr sdram1_config,r1 addis r1,0, 0x0000 /* set address map */ mtdcr icbs0_amap0,r0 mtdcr icbs0_amap1,r0// Pallas 1 bug mfspr r6,pvr addis r7,r0,0x4181 ori r7,r7,0x0890 // Pallas 1 cmplw r6,r7 beq mem_pass2 addis r3,0,0x0000 /* pallas 2 */ addis r4,0,0x0200 addis r5,0,0x2000 addis r6,0,0x2200 addis r7,0,0x01f0 b mem_pass1mem_pass2: addis r3,0,0x0000 /* pallas 1 */ addis r4,0,0x0080 addis r5,0,0xA000 addis r6,0,0xA080 addis r7,0,0x0070mem_pass1: addis r0,0,0 mtdcr sdram0_besr,r0 /* reset/unlock besr */ ori r0,r3,0x4000 mtdcr sdram0_br0,r0 ori r0,r4,0x4000 mtdcr sdram0_br1,r0 addis r0,0,0 mtdcr sdram0_br2,r0 mtdcr sdram0_br3,r0 mtdcr sdram0_cr0,r7 mtdcr sdram0_cr1,r7 addis r0,0,0 mtdcr sdram0_cr2,r0 mtdcr sdram0_cr3,r0 ori r0,r7,0x8000 /* enable sdram controllor */ mtdcr sdram0_cr0,r0 /* * SDRAM1 */ addis r0,0,0 mtdcr sdram1_besr,r0 /* reset/unlock besr */ ori r0,r5,0x4000 mtdcr sdram1_br0,r0 ori r0,r6,0x4000 mtdcr sdram1_br1,r0 addis r0,0,0 mtdcr sdram1_br2,r0 mtdcr sdram1_br3,r0 mtdcr sdram1_cr0,r7 mtdcr sdram1_cr1,r7 addis r0,0,0 mtdcr sdram1_cr2,r0 mtdcr sdram1_cr3,r0 ori r0,r7,0x8000 mtdcr sdram1_cr0,r0 //----------------------------------------------------------------------- // A few important regs first //----------------------------------------------------------------------- addi r0,0,0 mtsgr r0 mtdcwr r0 //----------------------------------------------------------------------- // Set up some machine state registers. //----------------------------------------------------------------------- addi r4, r0,0x0000 // initialize r4 to zero mtspr esr, r4 // clear Exception Syndrome Reg mttcr r4 // timer control register addis r4, r0,0xFFFF // set r4 to 0xFFFFFFFF (status in the ori r4, r4,0xFFFF // dbsr is cleared by setting bits to 1) mtdbsr r4 // clear/reset the dbsr mtdcr besr, r4 // clear Bus Error Syndrome Reg //----------------------------------------------------------------------- // Clear reservation bit. //----------------------------------------------------------------------- addis r10, r0,0x0000 lwarx r3, r10, r10 // get some data/set resv bit stwcx. r3, r10, r10 // store out and clear resv bit //----------------------------------------------------------------------- // Clear XER. //----------------------------------------------------------------------- addis r0, r0,0x0000 mtxer r0 //----------------------------------------------------------------------- // Mask off all interrupts in the universal interrupt controller //----------------------------------------------------------------------- addi r0,0,0 mtdcr u_uicer, r0 addis r1, r0,0x0000 addi r1, r1,0x3000 mtdcr u_uictr, r1 addis r1, r0,0x7BF7 // was 7bf8, and will be 7bf7 because of side effect of next addi ori r1, r1,0xFC01 // was f801, changed to support Pallas2 uart 1 //addi r1, r1,0xFC01 // was f801, changed to support Pallas2 uart 1 mtdcr u_uicpr, r1⌨️ 快捷键说明
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