enetloc.h

Ibmstb02500 miniboot 源码

/* openbios/arch/redwood5/enetloc.h, redbios */
/*-----------------------------------------------------------------------------+
|
|       This source code has been made available to you by IBM on an AS-IS
|       basis.  Anyone receiving this source is licensed under IBM
|       copyrights to use it in any way he or she deems fit, including
|       copying it, modifying it, compiling it, and redistributing it either
|       with or without modifications.  No license under IBM patents or
|       patent applications is to be implied by the copyright license.
|
|       Any user of this software should understand that IBM cannot provide
|       technical support for this software and will not be responsible for
|       any consequences resulting from the use of this software.
|
|       Any person who transfers this source code or any derivative work
|       must include the IBM copyright notice, this paragraph, and the
|       preceding two paragraphs in the transferred software.
|
|       COPYRIGHT   I B M   CORPORATION 1995
|       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+-----------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------+
|
|  File Name:   enetloc.h
|
|  Function:    Architecture local dependent defines of enetlib.
|
|  Author:      Jim Haller
|
|  Change Activity-
|
|  Date        Description of Change                                       BY
|  ---------   ---------------------                                       ---
|  13-Feb-01   Rewrite/Port to Redwood V / Pallas/ SMSC LAN91C1111         jfh
|  13-Aug-01   ********* SMSC LAN91C111 ******************************     jfh
|  13-Aug-01   Complete rewrite for SMSC 91111 for Redwood V/Pallas        jfh
|  30-Dec-01   Splitted from common include headers                        YYD
|
+-----------------------------------------------------------------------------*/
#ifndef _enetloc_h_
#define _enetloc_h_

struct net_device_stats {
        unsigned long   rx_packets;             /* total packets received       */
        unsigned long   tx_packets;             /* total packets transmitted    */
        unsigned long   rx_bytes;               /* total bytes received         */
        unsigned long   tx_bytes;               /* total bytes transmitted      */
        unsigned long   rx_errors;              /* bad packets received         */
        unsigned long   tx_errors;              /* packet transmit problems     */
        unsigned long   rx_dropped;             /* no space in linux buffers    */
        unsigned long   tx_dropped;             /* no space available in linux  */
        unsigned long   multicast;              /* multicast packets received   */
        unsigned long   collisions;

        /* detailed rx_errors: */
        unsigned long   rx_length_errors;
        unsigned long   rx_over_errors;         /* receiver ring buff overflow  */
        unsigned long   rx_crc_errors;          /* recved pkt with crc error    */
        unsigned long   rx_frame_errors;        /* recv'd frame alignment error */
        unsigned long   rx_fifo_errors;         /* recv'r fifo overrun          */
        unsigned long   rx_missed_errors;       /* receiver missed packet       */

        /* detailed tx_errors */
        unsigned long   tx_aborted_errors;
        unsigned long   tx_carrier_errors;
        unsigned long   tx_fifo_errors;
        unsigned long   tx_heartbeat_errors;
        unsigned long   tx_window_errors;

        /* for cslip etc */
        unsigned long   rx_compressed;
        unsigned long   tx_compressed;
};

struct enet_device {
        char                    name[9];
        unsigned long           base_addr;
        unsigned int            irq;
        unsigned int            interrupt;
        unsigned char           dev_addr[6];
        unsigned char           dma;
        unsigned int            tbusy;
        unsigned int            start;
/////// void                    *priv;  /* pointer to private data */
   struct       net_device_stats stats;
   int          packets_waiting;
   int          autoneg_active;
   unsigned int phyaddr;
   unsigned int phytype;
   unsigned int lastPhy18;
   unsigned int tcr_cur_mode;
   unsigned int rcr_cur_mode;
   unsigned int rpc_cur_mode;
   char         ctl_info[1024];
   int          ctl_swfdup;
   int          ctl_ephloop;
   int          ctl_miiop;
   int          ctl_autoneg;
   int          ctl_rfduplx;
   int          ctl_rspeed;
   int          ctl_afduplx;
   int          ctl_aspeed;
   int          ctl_lnkfail;
   int          ctl_forcol;
   int          ctl_filtcar;
   int          ctl_freemem;
   int          ctl_totmem;
   int          ctl_leda;
   int          ctl_ledb;
   int          ctl_chiprev;
        unsigned long           trans_start;
        int                     (*open)(struct enet_device *dev);
        int                     (*stop)(struct enet_device *dev);
        struct net_device_stats* (*get_stats)(struct enet_device *dev);
        void                     (*set_multicast_list)(struct enet_device *dev);
};


static const char * chip_ids[ 15 ] =  {
        NULL, NULL, NULL,
        /* 3 */ "SMC91C90/91C92",
        /* 4 */ "SMC91C94",
        /* 5 */ "SMC91C95",
        /* 6 */ "SMC91C96",
        /* 7 */ "SMC91C100",
        /* 8 */ "SMC91C100FD",
        /* 9 */ "SMC91C11xFD",
        NULL, NULL,
        NULL, NULL, NULL};

#define ENET_IO_ADDR          0x72000300

#define BANK_SELECT     0xE

// Base Address Register
/* BANK 1 */
#define BASE_REG        0x2

// Data Register
/* BANK 2 */
#define DATA_REG        0x0008

// Revision Register
/* BANK 3 */
#define REV_REG         0xA  /* ( hi: chip id   low: rev # ) */

// Memory Information Register
/* BANK 0  */
#define MIR_REG         0x8

// Receive/Phy Control Register
/* BANK 0  */
#define RPC_REG         0xA
#define RPC_SPEED       0x2000  // When 1 PHY is in 100Mbps mode.
#define RPC_DPLX        0x1000  // When 1 PHY is in Full-Duplex Mode
#define RPC_ANEG        0x0800  // When 1 PHY is in Auto-Negotiate Mode
#define RPC_LSXA_SHFT   5       // Bits to shift LS2A,LS1A,LS0A to lsb
#define RPC_LSXB_SHFT   2       // Bits to get LS2B,LS1B,LS0B to lsb
#define RPC_LED_100_10  (0x00)  // LED = 100Mbps OR's with 10Mbps link detect
#define RPC_LED_RES     (0x01)  // LED = Reserved
#define RPC_LED_10      (0x02)  // LED = 10Mbps link detect
#define RPC_LED_FD      (0x03)  // LED = Full Duplex Mode
#define RPC_LED_TX_RX   (0x04)  // LED = TX or RX packet occurred
#define RPC_LED_100     (0x05)  // LED = 100Mbps link dectect
#define RPC_LED_TX      (0x06)  // LED = TX packet occurred
#define RPC_LED_RX      (0x07)  // LED = RX packet occurred
#define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)

// Receive Control Register
/* BANK 0  */
#define RCR_REG         0x4
#define RCR_RX_ABORT    0x0001  // Set if a rx frame was aborted
#define RCR_PRMS        0x0002  // Enable promiscuous mode
#define RCR_ALMUL       0x0004  // When set accepts all multicast frames
#define RCR_RXEN        0x0100  // IFF this is set, we can receive packets
#define RCR_STRIP_CRC   0x0200  // When set strips CRC from rx packets
#define RCR_ABORT_ENB   0x0200  // When set will abort rx on collision
#define RCR_FILT_CAR    0x0400  // When set filters leading 12 bit s of carrier
#define RCR_SOFTRST     0x8000  // resets the chip

/* the normal settings for the RCR register : */
#define RCR_DEFAULT     (RCR_STRIP_CRC | RCR_RXEN)
#define RCR_CLEAR       0x0     // set it to a base state

// Counter Register
/* BANK 0  */
#define COUNTER_REG     0x0006

// Configuration Reg
/* BANK 1 */
#define CONFIG_REG      0x0
#define CONFIG_EXT_PHY  0x0200  // 1=external MII, 0=internal Phy
#define CONFIG_GPCNTRL  0x0400  // Inverse value drives pin nCNTRL
#define CONFIG_NO_WAIT  0x1000  // When 1 no extra wait states on ISA bus
#define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.

// Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
#define CONFIG_DEFAULT  (CONFIG_EPH_POWER_EN)


// Control Register
/* BANK 1 */
#define CTL_REG           0xC
#define CTL_RCV_BAD       0x4000 // When 1 bad CRC packets are received
#define CTL_AUTO_RELEASE  0x0800 // When 1 tx pages are released automatically
#define CTL_LE_ENABLE     0x0080 // When 1 enables Link Error interrupt
#define CTL_CR_ENABLE     0x0040 // When 1 enables Counter Rollover interrupt
#define CTL_TE_ENABLE     0x0020 // When 1 enables Transmit Error interrupt
#define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
#define CTL_RELOAD        0x0002 // When set reads EEPROM into registers
#define CTL_STORE         0x0001 // When set stores registers into EEPROM

// Transmit Control Register
/* BANK 0  */
#define TCR_REG         0x0     // transmit control register
#define TCR_ENABLE      0x0001  // When 1 we can transmit
#define TCR_LOOP        0x0002  // Controls output pin LBK
#define TCR_FORCOL      0x0004  // When 1 will force a collision
#define TCR_PAD_EN      0x0080  // When 1 will pad tx frames < 64 bytes w/0
#define TCR_NOCRC       0x0100  // When 1 will not append CRC to tx frames