elpaso.inc

Ibmstb02500 miniboot 源码

// openbios/m4/elpaso.inc, redbios, redbios_iii_1.0 2/8/99 17:48:26
//------------------------------------------------------------------------------+
//
//       This source code has been made available to you by IBM on an AS-IS
//       basis.  Anyone receiving this source is licensed under IBM
//       copyrights to use it in any way he or she deems fit, including
//       copying it, modifying it, compiling it, and redistributing it either
//       with or without modifications.  No license under IBM patents or
//       patent applications is to be implied by the copyright license.
//
//       Any user of this software should understand that IBM cannot provide
//       technical support for this software and will not be responsible for
//       any consequences resulting from the use of this software.
//
//       Any person who transfers this source code or any derivative work
//       must include the IBM copyright notice, this paragraph, and the
//       preceding two paragraphs in the transferred software.
//
//       COPYRIGHT   I B M   CORPORATION 1995
//       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
//-------------------------------------------------------------------------------
//-------------------------------------------------------------------------------
//
//  File Name:   elpaso.m4
//
//  Function:    elpaso specific regs.
//
//  Author:      Paul Gramann
//
//  Change Activity-
//
//  Date        Description of Change                                       BY
//  ---------   ---------------------                                       ---
//  13-Feb-98   Created                                                     pag
//  15-Jan-99   Added chip interconnect DCR regs                            pag
//  02-Feb-00   Added HSMC0 (second Mem controller)                         jfh
//              corrected u_uicpr comment polarity not parity               jfh
//-------------------------------------------------------------------------------
.set    BRH0          , 0x0070          // Bus Region Configuration Reg Hi 0
.set    BRH1          , 0x0071          // Bus Region Configuration Reg Hi 1
.set    BRH2          , 0x0072          // Bus Region Configuration Reg Hi 2
.set    BRH3          , 0x0073          // Bus Region Configuration Reg Hi 3
.set    BRH4          , 0x0074          // Bus Region Configuration Reg Hi 4
.set    BRH5          , 0x0075          // Bus Region Configuration Reg Hi 5
.set    BRH6          , 0x0076          // Bus Region Configuration Reg Hi 6
.set    BRH7          , 0x0077          // Bus Region Configuration Reg Hi 7

.set    BR0           , 0x0080          // Bus Region Configuration Reg 0
.set    BR1           , 0x0081          // Bus Region Configuration Reg 1
.set    BR2           , 0x0082          // Bus Region Configuration Reg 2
.set    BR3           , 0x0083          // Bus Region Configuration Reg 3
.set    BR4           , 0x0084          // Bus Region Configuration Reg 4
.set    BR5           , 0x0085          // Bus Region Configuration Reg 5
.set    BR6           , 0x0086          // Bus Region Configuration Reg 6
.set    BR7           , 0x0087          // Bus Region Configuration Reg 7

.set    BEAR          , 0x0090          // Bus Error Addr
.set    BESR          , 0x0091          // Bus error syndrome
.set    BESR0         , 0X0091          // Bus error syndrome
.set    BESRS         , 0x0093          // Bus error syndrome
.set    BESR0S        , 0x0093          // Bus error syndrome
.set    BIUCR         , 0x009A          // Bus Interface Unit Control reg

.set    u_uicsr ,       0x040           //       /* status register         rc*/
.set    u_uicer   ,     0x042           //       /* enable register           */
.set    u_uiccr   ,     0x043           //       /* critical register         */
.set    u_uicpr   ,     0x044           //       /* polarity register         */
.set    u_uictr   ,     0x045           //       /* triggering register       */
.set    u_uicmsr  ,     0x046           //       /*rmasked status register    */
.set    u_uicvr   ,     0x047           //       /*rvector register           */
.set    u_uicvcr  ,     0x048           //       /*wenable config register    */

.set    hsmc_mcgr   ,   0x1c0           //       /* HSMC global register      */
.set    hsmc_mcbesr ,   0x1c1           //       /* bus error status register */
.set    hsmc_mcbear ,   0x1c2           //       /* bus error address register*/
.set    hsmc_mcbr0  ,   0x1c4           //       /* SDRAM sub-ctrl bank reg 0 */
.set    hsmc_mccr0  ,   0x1c5           //       /* SDRAM sub-ctrl ctrl reg 0 */
.set    hsmc_mcbr1  ,   0x1c7           //       /* SDRAM sub-ctrl bank reg 1 */
.set    hsmc_mccr1  ,   0x1c8           //       /* SDRAM sub-ctrl ctrl reg 1 */
.set    hsmc_mcdata ,   0x1d2           //       /* data register             */
.set    hsmc_mccrr  ,   0x1d3           //       /* refresh register          */

.set    hsmc0_mcgr   ,   0x1e0          //       /* HSMC global register      */
.set    hsmc0_mcbesr ,   0x1e1          //       /* bus error status register */
.set    hsmc0_mcbear ,   0x1e2          //       /* bus error address register*/
.set    hsmc0_mcbr0  ,   0x1e4          //       /* SDRAM sub-ctrl bank reg 0 */
.set    hsmc0_mccr0  ,   0x1e5          //       /* SDRAM sub-ctrl ctrl reg 0 */
.set    hsmc0_mcbr1  ,   0x1e7          //       /* SDRAM sub-ctrl bank reg 1 */
.set    hsmc0_mccr1  ,   0x1e8          //       /* SDRAM sub-ctrl ctrl reg 1 */
.set    hsmc0_mcdata ,   0x1f2          //       /* data register             */
.set    hsmc0_mccrr  ,   0x1f3          //       /* refresh register          */

.set    cic0_cr     ,   0x30              //  Chip interconnect control reg
.set    cic0_vcr    ,   0x33              //  Chip interconnect video control reg
.set    cic0_sel3   ,   0x35              //  Chip interconnect select 2 reg
.set	cbs0_cr	    ,	0x10		  //  Crossbar config, must set to 0x00000002


/* Add some Architecture specific defines 
|  These definitions change across Vesta and Pallas
|  Pallas has 16KB, Vesta has 8KB
*/
.set    DCACHE_LINE_SIZE,        0x20
.set    DCACHE_NUM_LINES,        0x80      // # of dcache congruence classes
.set    DCACHE_PPC_SET_SIZE ,    0x1000    // Dcache_size/(num of sets assoc)