gfxlib.c

Ibmstb02500 miniboot 源码

    {0xc0,   0xc0,   0xc0 },   //  240
    {0xc8,   0xc8,   0xc8 },   //  241
    {0xd0,   0xd0,   0xd0 },   //  242
    {0xd8,   0xd8,   0xd8 },   //  243
    {0xe0,   0xe0,   0xe0 },   //  244
    {0xe8,   0xe8,   0xe8 },   //  245
    {0xf0,   0xf0,   0xf0 },   //  246
    {0xf8,   0xf8,   0xf8 },   //  247
    {0xff,   0xff,   0xff },   //  248

    // from 249 to 255, 7 color rainbow
    {0x00,   0x00,   0xff },   //  249
    {0x00,   0xff,   0x00 },   //  250
    {0x00,   0xff,   0xff },   //  251
    {0xff,   0x00,   0x00 },   //  252
    {0xff,   0x00,   0xff },   //  253
    {0xff,   0xff,   0x00 },   //  254
    {0xff,   0xff,   0xff }    //  255
};

#ifdef __GNUC__
#pragma pack()
#endif

/*----------------------------------------------------------------------------+
| Video decoder.  Suspect 0x179, 0x169, 0x16a, 0x152 (rc).
+----------------------------------------------------------------------------*/
#define v_c_cntl        0x140               /* control decoder operation     */
#define v_c_mode        0x141               /* video operational mode        */
#define v_osd_m         0x151               /* OSD mode control              */
#define v_dispm         0x154               /* operational mode for Disp     */
#define v_dispd         0x155               /* setting for 'Sync' delay      */
#define v_dispbor       0x158               /* display left/top border       */
#define v_osd_gla       0x159               /* Graphics plane link addr      */
#define v_osd_ila       0x15A               /* Image plane link addr         */
#define v_osd_cla       0x15C               /* Cursor link addr              */
#define v_imgbase       0x16D               /* Image plane base address      */
#define v_grbase        0x16E               /* Graphic plane base address    */
#define v_m_seg0        0x175               /* segment address 0             */
#define v_m_seg1        0x176               /* segment address 1             */
#define v_m_seg2        0x177               /* segment address 2             */
#define v_m_seg3        0x178               /* segment address 3             */
#define v_curbase       0x17A               /* Cursor base addr              */
#define v_tl_border     0x17B               /* top left border               */
#define v_tr_dly        0x17C               /* transparency gate delay       */
#define v_small_board   0x17D               /* left/top small pict. bord.    */
#define v_hv_zoom       0x17E               /* hor/ver zoom window           */


#define DECOD_RESET_CHIP                0x04000000
#define DECOD_OSD_MODE_OSD_G_ENABLE     0x00000048 /* turn on animation bit due to problem with Vesta */
#define DECOD_OSD_MODE_OSD_G_BMLA	0x00000020
#define DECOD_OSD_MODE_OSD_G_BLEND	0x00000010
#define DECOD_OSD_MODE_OSD_I_ENABLE	0x00004000
#define DECOD_OSD_MODE_OSD_I_BMLA	0x00002000
#define DECOD_OSD_MODE_DECIMATION	0x00001000

#define DECOD_OSD_LINK_ADDR_RES		32
#define DECOD_MEM_ALIGN			128

#define DECOD_DISP_MODE_BK_MASK         0xFFFF0000
#define DECOD_DISP_MODE_BK_Y_MASK       0xFF000000
#define DECOD_DISP_MODE_BK_CB_MASK      0x00F00000
#define DECOD_DISP_MODE_BK_CR_MASK      0x000F0000
#define DECOD_DISP_MODE_BK_BLACK        0x00880000
#define DECOD_DISP_MODE_COMP_BLANKING   0x00002000
#define DECOD_DISP_MODE_HSC_VSC         0x00004000
#define DECOD_DISP_MODE_SYNC_TRAILING   0x00006000
#define DECOD_DISP_MODE_CCIR_656        0x0000A000
#define DECOD_DISP_MODE_SYNC_LEADING    0x0000E000
#define DECOD_DISP_MODE_HSC_POL_ACT_HI  0x00001000
#define DECOD_DISP_MODE_VSC_POL_HIGH    0x00000800
#define DECOD_DISP_MODE_PAL_MODE        0x00000400
#define DECOD_DISP_MODE_TRANS_POL_LOW   0x00000200
#define DECOD_DISP_MODE_YCBCR_CLIP_254  0x00000000
#define DECOD_DISP_MODE_YCBCR_NO_CLIP   0x00000040
#define DECOD_DISP_MODE_YCBCR_CLIP_253  0x00000080
#define DECOD_DISP_MODE_YCBCR_CLIP      0x000000C0
#define DECOD_DISP_MODE_NORM_DISP       0x00000000
#define DECOD_DISP_MODE_BOTTOM_ONLY     0x00000010
#define DECOD_DISP_MODE_TOP_ONLY        0x00000020
#define DECOD_DISP_MODE_FIRST_ONLY      0x00000030
#define DECOD_DISP_MODE_LETTERBOX_DISP  0x00000002
#define DECOD_DISP_MODE_1_2_h_v         0x00000006
#define DECOD_DISP_MODE_1_4_h_v         0x00000008
#define DECOD_DISP_MODE_2x              0x0000000A
#define DECOD_DISP_MODE_DISABLE_EXP     0x0000000E
#define DECOD_DISP_MODE_MASK            0x0000000E
#define DECOD_DISP_MODE_16_9_MONITOR    0x00000001

#define DECOD_OSD_MODE_EDAF		0x00200000
#define	DECOD_OSD_MODE_AFDT_0		0x00000000	
#define	DECOD_OSD_MODE_AFDT_16		0x00040000
#define	DECOD_OSD_MODE_AFDT_32		0x00080000
#define	DECOD_OSD_MODE_AFDT_48		0x000c0000

#define DENC_INTERNAL           0x00004714
#define DENC_EXTERNAL           0x00004714

/*----------------------------------------------------------------------------+
| Definition for special setstat functions
+----------------------------------------------------------------------------*/
#define DENC_COLOR_BAR_ON       0x1
#define DENC_COLOR_BAR_OFF      0x2
#define DENC_NTSC_MODE          0x3
#define DENC_PAL_MODE           0x4
#define DENC_SECAM_MODE         0x5
#define DENC_COLOR_BAR_RAMP     0x6
#define DENC_PAL_M_MODE         0x7
#define DENC_PAL_N_MODE         0x8
#define DENC_COLOR_BAR_PLUGE    0x9

#define DENC_CR1        0x131                   /* control register 1        */

#define OSD_DATA_START_OFFSET    4096 /*(OSD_HEADER_SIZE + OSD_CLUT_SIZE) */

#define VIDEO_RAM_VESTA_OFFSET  (0x200000)
#define VIDEO_RAM_ADDRESS_VESTA  (VIDEO_RAM_ADDRESS+VIDEO_RAM_VESTA_OFFSET)	// work around of dirty Vesta video bug 

struct boot_logo_buffer_info boot_logo_buffer;  // for extern use

static osdhdr_t	     *osd_ctl      = (osdhdr_t *)VIDEO_RAM_ADDRESS_VESTA;
static unsigned char *video_buffer = (unsigned char *)(VIDEO_RAM_ADDRESS_VESTA + OSD_DATA_START_OFFSET);


char *bios_tv_fmt_str[NUMBER_TV_FMT] = { "NTSC", "PAL/B/G/I", "PAL/M",  "PAL/N"};

static void init_gfx_hardware(int fmt)
{
	unsigned long reg;
#if 0
	/* reset decoder */
	reg=MF_DCR(cic_cr);/* set cic control_register bit 5 ='1'*/
	MT_DCR(cic_cr,reg|DECOD_RESET_CHIP);
	sleep_on_time(1);/* wait at least 10us */
	MT_DCR(cic_cr, reg &(~DECOD_RESET_CHIP));/* set cic control_register bit 5 ='0'*/
#endif

	MT_DCR(v_c_cntl,0);
	/* set segment register */
	/* 1MB of the SDRAM should be enough in all our case */
	MT_DCR(v_m_seg0, ((VIDEO_RAM_ADDRESS & 0xffc00000) >>20) | (2<<12));
//	MT_DCR(v_m_seg0, (0xa0000000 >>20) | (4<<12)); // test

	/* set video chip mode 
	MT_DCR(v_c_mode,0x00000000 );*/
	MT_DCR(v_osd_m, 0);
#if 0
	/* 
	 * Define top and left borders, and display delay.  Set top border in the
	 * letterbox mode (number of lines from the top of the display). 
	 */
	MT_DCR(v_dispbor, 0);

#endif
	MT_DCR(v_dispd,DENC_INTERNAL); 

	/*start video proc, disable sync, enable video
	MT_DCR(v_c_cntl,DECOD_CHIP_CONTROL_SVP|DECOD_CHIP_CONTROL_DIS_SYNC|
	DECOD_CHIP_CONTROL_BLANK_VID);*/

	MT_DCR(v_grbase, (unsigned long) (VIDEO_RAM_VESTA_OFFSET)/DECOD_MEM_ALIGN); // fixed from 0x003fffff
	MT_DCR(v_osd_gla,0);
	
	reg = MF_DCR(v_osd_m);
        MT_DCR(v_osd_m, reg&(~DECOD_OSD_MODE_OSD_G_ENABLE)); 
        
	if (TV_FMT_PAL == fmt || TV_FMT_PAL_M == fmt || TV_FMT_PAL_N == fmt)  // PAL mode 
	{
		MT_DCR(v_dispm,
			DECOD_DISP_MODE_BK_BLACK|
			DECOD_DISP_MODE_TRANS_POL_LOW|
			DECOD_DISP_MODE_PAL_MODE|DECOD_DISP_MODE_SYNC_LEADING|0 /*16:9*/);  
	}
	else
	{
		MT_DCR(v_dispm,
			DECOD_DISP_MODE_BK_BLACK|
			DECOD_DISP_MODE_TRANS_POL_LOW|
			DECOD_DISP_MODE_SYNC_LEADING|0 /*16:9*/);
	}

	reg = MF_DCR(v_osd_m);
	MT_DCR(v_osd_m, reg | DECOD_OSD_MODE_OSD_G_ENABLE | DECOD_OSD_MODE_DECIMATION | DECOD_OSD_MODE_OSD_G_BMLA |
		DECOD_OSD_MODE_EDAF | DECOD_OSD_MODE_AFDT_0);
	 
}

static void init_denc(int fmt)
{
   unsigned long reg;
   reg = MF_DCR(DENC_CR1);

   switch(fmt) {
#ifdef BIOS_OLIVIA
      case TV_FMT_PAL:  // PAL
	 MT_DCR(DENC_CR1,0x81180040);
         break;
      case TV_FMT_PAL_M:  // PAL/M
	 MT_DCR(DENC_CR1,0x82180040);
         break;
      case TV_FMT_PAL_N:  // PAL/N
	 MT_DCR(DENC_CR1,0x85180040);
         break;
      case TV_FMT_NTSC:  // NTSC
      default:
	 MT_DCR(DENC_CR1,0x80180040);
         break;
#else  // BIOS_REDWOOD4
      case TV_FMT_PAL:  // PAL
	 MT_DCR(DENC_CR1,0x81100040);
         break;
      case TV_FMT_PAL_M:  // PAL/M
	 MT_DCR(DENC_CR1,0x82100040);
         break;
      case TV_FMT_PAL_N:  // PAL/N
	 MT_DCR(DENC_CR1,0x85100040);
         break;
      case TV_FMT_NTSC:  // NTSC
      default:
	 MT_DCR(DENC_CR1,0x80100040);
         break;
#endif
   }
}


static void gfx_osi_rgb2ycbcr(unsigned char r, unsigned char g,  unsigned char b,  unsigned char *y, unsigned char *cb, unsigned char *cr)
{
    // Y  =  0.257*R + 0.504*G + 0.098*B + 16
    // CB = -0.148*R - 0.291*G + 0.439*B + 128
    // CR =  0.439*R - 0.368*G - 0.071*B + 128
    *y  = (unsigned char)((8432*(unsigned long)r + 16425*(unsigned long)g + 3176*(unsigned long)b + 16*32768)>>15);
    *cb = (unsigned char)((128*32768 + 14345*(unsigned long)b - 4818*(unsigned long)r -9527*(unsigned long)g)>>15);
    *cr = (unsigned char)((128*32768 + 14345*(unsigned long)r - 12045*(unsigned long)g-2300*(unsigned long)b)>>15);
}


int gfx_set_palette(unsigned char *pal, unsigned int start, int count)
{
   unsigned int i;
   if(start > 255) return -1;
   if(start + count > 256) count = 256-start;
   for(i=0; i<256; i++)
   {
   	unsigned char y,u,v;
   	gfx_osi_rgb2ycbcr(pal[i*3], pal[i*3+1], pal[i*3+2], &y, &u, &v);
   	osd_ctl->palette[i] = (((unsigned short)y&0xfc)<< 8) | (((unsigned short)u&0xf0)<<2) | (((unsigned short)v&0xf0)>>2);
   }
   return i;
} 

#ifdef DEBUG
void mdump(void *ptr, int s, char *pp)
    {
        int i,j;
        s1printf("%s\n", pp);
        for(i=0; i<s; i+=16)
        {
           s1printf("%08x  ", i+(char *)ptr);
           for(j=0; j<16; j++) 
              s1printf("%02x ", (int)*((unsigned char *)ptr+i+j));
           s1printf("\n");
        }
    }
#endif

int init_graphics()
{
    if(!confdata.enable_boot_logo ||
       confdata.video_width > BOOTLOGO_MAXWIDTH ||
       confdata.video_height > BOOTLOGO_MAXHEIGHT ||
       confdata.video_left >  BOOTLOGO_MAXWIDTH/2 ||
       confdata.video_upper > BOOTLOGO_MAXHEIGHT/2  )
    {
    	// confdata is not ok or video is disabled
    	return -1;
    }
    
    boot_logo_buffer.base = (unsigned long)video_buffer;
    boot_logo_buffer.xsize = (unsigned short)confdata.video_width;
    boot_logo_buffer.ysize = (unsigned short)confdata.video_height;
    boot_logo_buffer.line_size = (unsigned short)(confdata.video_width+3) & 0xfffffffc;
    boot_logo_buffer.video_fmt = BOARD_CFG_EXT_VFMT_RGB8;
    
    
    memset(video_buffer, 0, boot_logo_buffer.line_size*boot_logo_buffer.ysize);
    memset(osd_ctl, 0, sizeof(osdhdr_t));
   
    osd_ctl->color_table_update	= 1;
    osd_ctl->region_hsize	= boot_logo_buffer.line_size/4;
    osd_ctl->region_vsize	= boot_logo_buffer.ysize/2;
    osd_ctl->high_color		= 1; // 8 bit palette mode
    osd_ctl->color_resolution	= 0; // 8 bit palette mode
    osd_ctl->start_row		= confdata.video_upper/2;  // div by 2 ?
    osd_ctl->start_column	= confdata.video_left/2;   // div by 4 ?
    osd_ctl->link_addr		= 0;  // we have only one region start at 0

    osd_ctl->h_ext		= 1;  // ext header 2 is also used
    osd_ctl->extlink_addr	= (OSD_DATA_START_OFFSET)/4;
    osd_ctl->anti_flicker	= 2;		
    
    // init palette
    gfx_set_palette((unsigned char *)webpalette, 0, 256);

#ifdef DEBUG
    s1printf("Before init denc\n");
#endif    
    init_denc((int)confdata.video_format);

#ifdef DEBUG
    s1printf("Before init gfx_hdw\n");
#endif    
    init_gfx_hardware((int)confdata.video_format);

#ifdef DEBUG
    s1printf("Before fill %08x\n", video_buffer);
#endif    

#ifdef DEBUG
    {
    	int i, j;
    	s1printf("Fill screen with color bar\n");
    	for(i=0; i<boot_logo_buffer.ysize; i++)
    	  for(j=0; j<boot_logo_buffer.xsize; j++)
    	    {
    	    	*(video_buffer + i*boot_logo_buffer.line_size + j) = j/2;
    	    }
    }
    s1printf("Before dump\n");
    mdump(osd_ctl, 64,"header");
    mdump(video_buffer, 64, "buffer");
#endif

    return 0;
}