initbrd.s

Ibmstb02500 miniboot 源码

// openbios/arch/vesta/redwood4/initbrd.s, stbbios
//------------------------------------------------------------------------------+
//
//       This source code has been made available to you by IBM on an AS-IS
//       basis.  Anyone receiving this source is licensed under IBM
//       copyrights to use it in any way he or she deems fit, including
//       copying it, modifying it, compiling it, and redistributing it either
//       with or without modifications.  No license under IBM patents or
//       patent applications is to be implied by the copyright license.
//
//       Any user of this software should understand that IBM cannot provide
//       technical support for this software and will not be responsible for
//       any consequences resulting from the use of this software.
//
//       Any person who transfers this source code or any derivative work
//       must include the IBM copyright notice, this paragraph, and the
//       preceding two paragraphs in the transferred software.
//
//       COPYRIGHT   I B M   CORPORATION 1995
//       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
//-------------------------------------------------------------------------------
//
//  File Name:   initbrd.s
//
//  Function:    This is the architecture dependent init code for the ROM Monitor
//               shipped with the IBM REDWOOD4 / STB03xxx (Vesta).
//
//  Author:      Bill DeStein (initially)
//
//  Change Activity-
//
//  Date        Description of Change                                       BY
//  ---------   ---------------------                                       ---
//  18-Mar-98   Ported to Redwood from Hawthorne                            pag
//  25-Mar-98   bumped level for dccr fix                                   pag
//  26-Mar-98   bumped level for initializing sdram                         pag
//  09-Apr-98   Fixed interrupt handling problem                            pag
//  14-Jan-99   Porting to Redwood III                                      pag
//  31-Mar-99   Fixed code bug in data_ramc using r0 to move r3->r4         pag
//  02-Apr-99   Changed code to support RIT-B & RIT-A (serial clock)        pag
//  02-Feb-00   Ported to Redwood IV Vesta STB                              jfh
//  30-Dec-01   Splitted to architecture depdendent part from entry.s       YYD
//
//-------------------------------------------------------------------------------

// Tristate for other masters, disable ready time outs
//
        xor     r0,r0,r0
        oris    r1,r0,0xA000	
        mtdcr   BIUCR,r1

	xor	r0,r0,r0
	ori	r0,r0, 0x0002
	mtdcr   cbs0_cr, r0
	 
        //-----------------------------------------------------------------------
        // Set up default chip interconnect
        //-----------------------------------------------------------------------
        xor     r0,r0,r0
        addis   r0,r0,0xd080
        ori     r0,r0,0x0448
        mtdcr   cic0_cr,r0

        xor     r0,r0,r0
        lis     r0,0x1150              		/* r10 <- CIC SEL3 Reg val  */
        mtdcr   cic0_sel3, r0

        xor     r0,r0,r0
        lis     r0, 0x0063               /* r10 <- CIC Vid C-Reg val */
        ori     r0,r0,0x1700
        mtdcr   cic0_vcr,r0
        

// Initialize Bank 0 for 16 bit Flash
//
        xor     r0,r0,r0             //
        mtdcr   brh0,r0                // Set Bus Region Config Hi reg 0
        addis   r0,r0,0xFC58          // was fff8
        ori     r0,r0,0xBFFE          //
        mtdcr   br0,r0                 // Set Bus Region Config reg 0
//
// Initialize Bank 2 for Xilinx
//
        xor     r0,r0,r0             //
        mtdcr   brh2,r0                // Set Bus Region Config Hi reg 7
        addis   r0,r0,0x207c          //
        ori     r0,r0,0xcfbe          //  was 0xffbf          // (with ready enabled)
        mtdcr   br2,r0                 // Set Bus Region Config reg 7

//
// Disable unused banks.
//
        addis   r6,r0,0xFF00
        ori     r6,r6,0xBFFF
        xor     r0,r0,r0             //

        mtdcr   brh3,r0
        mtdcr   br3,r6

        mtdcr   brh4,r0
        mtdcr   br4,r6

        mtdcr   brh5,r0
        mtdcr   br5,r6

        mtdcr   brh6,r0
        mtdcr   br6,r6

        mtdcr   brh7,r0
        mtdcr   br7,r6

        //-----------------------------------------------------------------------
        // Invalidate i-cache and d-cache TAG arrays.
        //-----------------------------------------------------------------------
        addi    r7,r0,128            // set r7 to # of lines in data cache
                                        // for loop count- romeo has 64 lines
..dcache:
        addi    r6,0,0x0000            // clear GPR 6
        mtctr   r7                     // set loop ctr
..dcloop:
        dccci   0,r6                   // invalidate line
        addi    r6,r6,0x20            // bump to next line
        bdnz    ..dcloop
..icache:
        addi    r6,0,0x0000            // clear GPR 6
..icloop:
        iccci   0,r6                   // invalidates all i-cache

// Cache Enable
        addis   r1,r0,0x8000
        addi    r1,r1,0x0001
        mticcr  r1

        //-----------------------------------------------------------------------
        // Initialize GPIOs to minimum options needed for OpenBIOS
        //-----------------------------------------------------------------------
        addis   r4,r0,0x4006            // GPIO 0
        addis   r0,r0,0x0c02
        ori     r0,r0,0x0004
        stw     r0,0x0004(r4)

        addis   r0,r0,0x01a0
        ori     r0,r0,0x0004
        stw     r0,0x0008(r4)

        addis   r0,r0,0x0000
        ori     r0,r0,0x000f
        stw     r0,0x000c(r4)

        addis   r0,r0,0x01a0
        ori     r0,r0,0x0000
        stw     r0,0x0010(r4)

        addis   r0,r0,0x0000
        ori     r0,r0,0x000f
        stw     r0,0x0014(r4)

        addis   r0,r0,0x0000
        ori     r0,r0,0x0000
        stw     r0,0x0018(r4)

        addis   r0,r0,0x0000
        ori     r0,r0,0x0151
        stw     r0,0x0030(r4)

        addis   r0,r0,0x0000
        ori     r0,r0,0x0000
        stw     r0,0x0034(r4)

        //-----------------------------------------------------------------------
        // Configure Minimal Xilinx needed for OpenBIOS to work
        //-----------------------------------------------------------------------
        addis   r3,r0,0x7204             // Mux base address

        addi    r0,r0,0x0840             // Enable UART2 MUX2
        sth     r0,0x0(r3)               // Update Xilinx mux reg 0

        addi    r0,r0,0x0440             // Enable UART2 DCR GPIO & SYS CLK GPIO
        sth     r0,0x4(r3)               // Update Xilinx mux reg 2

        addi    r0,r0,0x4800             // Enable Serial2 & Ethernet Reset
        sth     r0,0xa(r3)               // Update Xilinx mux reg 5

        addi    r0,r0,0x0000
        sth     r0,0xc(r3)               // Update Xilinx mux reg 6

        addi    r0,r0,-1
        sth     r0,0xe(r3)               // Clock all Xilinx mux regs


//-----------------------------------------------------------------------
// Configure SDRAM 0
//-----------------------------------------------------------------------

#if (RAM_BANK_0_SIZE == 0x02000000)  // 32MB config
  .set SDRAM0_CR,     0x80f0
  .set SDRAM0_MCBR0,  0x000d6d55
  .set SDRAM0_MCBR1,  0x010d6d55
#elif  (RAM_BANK_0_SIZE == 0x01000000)  // 16MB config
  .set SDRAM0_CR,     0x8070
  .set SDRAM0_MCBR0,  0x000d2d55
  .set SDRAM0_MCBR1,  0x008d2d55
#else
  #error "RAM bank size not supported//"
#endif

#if (RAM_BANK_1_SIZE == 0x02000000)  // 32MB config
  .set SDRAM1_CR,     0x80f0
  .set SDRAM1_MCBR0,  0xA00d6d55
  .set SDRAM1_MCBR1,  0xA10d6d55
#elif  (RAM_BANK_1_SIZE == 0x01000000)  // 16MB config
  .set SDRAM1_CR,     0x8070
  .set SDRAM1_MCBR0,  0xA00d2d55
  .set SDRAM1_MCBR1,  0xA08d2d55
#else
  #error "RAM bank size not supported//"
#endif

        xor     r0,r0,r0
        addis   r0,r0,0x06c0
        ori     r0,r0,0x0000
        mtdcr   hsmc0_mcgr,r0

        xor     r0,r0,r0
        addis   r0,r0,SDRAM0_MCBR0@h
        ori     r0,r0,SDRAM0_MCBR0@l     
        mtdcr   hsmc0_mcbr0,r0

        xor     r0,r0,r0
        addis   r0,r0,SDRAM0_MCBR1@h
        ori     r0,r0,SDRAM0_MCBR1@l     
        mtdcr   hsmc0_mcbr1,r0

        xor     r0,r0,r0
        addis   r0,r0,(SDRAM0_CR + 0x0007)
        ori     r0,r0,0x0000
        mtdcr   hsmc0_mccr0,r0

        xor     r0,r0,r0
        addis   r0,r0,(SDRAM0_CR + 0x0007)
        ori     r0,r0,0x0000
        mtdcr   hsmc0_mccr1,r0

        xor     r0,r0,r0
        addis   r0,r0,(SDRAM0_CR + 0x0008)
        ori     r0,r0,0x0000
        mtdcr   hsmc0_mccr0,r0

        xor     r0,r0,r0
        addis   r0,r0,(SDRAM0_CR + 0x0008)
        ori     r0,r0,0x0000
        mtdcr   hsmc0_mccr1,r0

        xor     r0,r0,r0
        addis   r0,r0,0x0037
        ori     r0,r0,0x0000
        mtdcr   hsmc0_mcdata,r0

        xor     r0,r0,r0
        addis   r0,r0,(SDRAM0_CR + 0x0000)
        ori     r0,r0,0x8000
        mtdcr   hsmc0_mccr0,r0

        xor     r0,r0,r0
        addis   r0,r0,(SDRAM0_CR + 0x0000)
        ori     r0,r0,0x8000
        mtdcr   hsmc0_mccr1,r0

        xor     r0,r0,r0
        addis   r0,r0,0x0fe1
        ori     r0,r0,0x0000
        mtdcr   hsmc0_mccrr,r0

        xor     r0,r0,r0
        addis   r0,r0,0x6c00
        ori     r0,r0,0x0000
        mtdcr   hsmc0_mcgr,r0

//-----------------------------------------------------------------------
// Configure SDRAM 1
//-----------------------------------------------------------------------
        xor     r0,r0,r0
        addis   r0,r0,0x06c0
        ori     r0,r0,0x0000
        mtdcr   hsmc_mcgr,r0

        xor     r0,r0,r0
        addis   r0,r0,SDRAM1_MCBR0@h
        ori     r0,r0,SDRAM1_MCBR0@l     
        mtdcr   hsmc_mcbr0,r0

        xor     r0,r0,r0
        addis   r0,r0,SDRAM1_MCBR1@h
        ori     r0,r0,SDRAM1_MCBR1@l     
        mtdcr   hsmc_mcbr1,r0

        xor     r0,r0,r0
        addis   r0,r0,(SDRAM1_CR + 0x0007)
        ori     r0,r0,0x0000
        mtdcr   hsmc_mccr0,r0

        xor     r0,r0,r0
        addis   r0,r0,(SDRAM1_CR + 0x0007)
        ori     r0,r0,0x0000
        mtdcr   hsmc_mccr1,r0

        xor     r0,r0,r0
        addis   r0,r0,(SDRAM1_CR + 0x0008)
        ori     r0,r0,0x0000
        mtdcr   hsmc_mccr0,r0

        xor     r0,r0,r0
        addis   r0,r0,(SDRAM1_CR + 0x0008)
        ori     r0,r0,0x0000
        mtdcr   hsmc_mccr1,r0

        xor     r0,r0,r0
        addis   r0,r0,0x0037
        ori     r0,r0,0x0000
        mtdcr   hsmc_mcdata,r0

        xor     r0,r0,r0
        addis   r0,r0,(SDRAM1_CR + 0x0000)
        ori     r0,r0,0x8000
        mtdcr   hsmc_mccr0,r0

        xor     r0,r0,r0
        addis   r0,r0,(SDRAM1_CR + 0x0000)
        ori     r0,r0,0x8000
        mtdcr   hsmc_mccr1,r0

        xor     r0,r0,r0
        addis   r0,r0,0x0fe1
        ori     r0,r0,0x0000
        mtdcr   hsmc_mccrr,r0

        xor     r0,r0,r0
        addis   r0,r0,0x6c00
        ori     r0,r0,0x0000
        mtdcr   hsmc_mcgr,r0


        //-----------------------------------------------------------------------
        // A few important regs first
        //-----------------------------------------------------------------------
        addi    r0,0,0
        mtsgr   r0
        mtdcwr  r0

        //-----------------------------------------------------------------------
        // Set up some machine state registers.
        //-----------------------------------------------------------------------
        addi    r4,r0,0x0000          // initialize r4 to zero
        mtspr   esr,r4                 // clear Exception Syndrome Reg
        mttcr   r4                     // timer control register
        addis   r4,r0,0xFFFF          // set r4 to 0xFFFFFFFF (status in the
        ori     r4,r4,0xFFFF          // dbsr is cleared by setting bits to 1)
        mtdbsr  r4                     // clear/reset the dbsr
        mtdcr   besr,r4                // clear Bus Error Syndrome Reg

        //-----------------------------------------------------------------------
        // Clear reservation bit.
        //-----------------------------------------------------------------------
        addis   r10,r0,0x0000
        lwarx   r3,r10,r10           // get some data/set resv bit
        stwcx.  r3,r10,r10           // store out and clear resv bit

        //-----------------------------------------------------------------------
        // Clear XER.
        //-----------------------------------------------------------------------
        addis   r0,r0,0x0000
        mtxer   r0

        //-----------------------------------------------------------------------
        // Mask off all interrupts in the universal interrupt controller
        //-----------------------------------------------------------------------
        addi    r0,0,0
        mtdcr   u_uicer,r0