elpaso.inc

Ibmstb02500 miniboot 源码

// openbios/m4/elpaso.inc, redbios, redbios_iii_1.0 2/8/99 17:48:26
//------------------------------------------------------------------------------+
//
//       This source code has been made available to you by IBM on an AS-IS
//       basis.  Anyone receiving this source is licensed under IBM
//       copyrights to use it in any way he or she deems fit, including
//       copying it, modifying it, compiling it, and redistributing it either
//       with or without modifications.  No license under IBM patents or
//       patent applications is to be implied by the copyright license.
//
//       Any user of this software should understand that IBM cannot provide
//       technical support for this software and will not be responsible for
//       any consequences resulting from the use of this software.
//
//       Any person who transfers this source code or any derivative work
//       must include the IBM copyright notice, this paragraph, and the
//       preceding two paragraphs in the transferred software.
//
//       COPYRIGHT   I B M   CORPORATION 1995
//       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
//-------------------------------------------------------------------------------
//-------------------------------------------------------------------------------
//
//  File Name:   elpaso.m4
//
//  Function:    elpaso specific regs.
//
//  Author:      Paul Gramann
//
//  Change Activity-
//
//  Date        Description of Change                                       BY
//  ---------   ---------------------                                       ---
//  13-Feb-98   Created                                                     pag
//  15-Jan-99   Added chip interconnect DCR regs                            pag
//  02-Feb-00   Added HSMC0 (second Mem controller)                         jfh
//              corrected u_uicpr comment polarity not parity               jfh
//  04-12-02    Modifications for Vulcan/Redwood6                           vk
//-------------------------------------------------------------------------------

.set    cbscr  ,        0x0010          // Cross-bar switch configuration register
.set    dcr_34 ,        0x034           // Hidden DCR but has to be set.
.set    biucr  ,        0x009A          // Bus Interface Unit Control Reg    

.set    u_uicsr ,       0x040           //       /* status register         rc*/
.set    u_uicer   ,     0x042           //       /* enable register           */
.set    u_uiccr   ,     0x043           //       /* critical register         */
.set    u_uicpr   ,     0x044           //       /* polarity register         */
.set    u_uictr   ,     0x045           //       /* triggering register       */
.set    u_uicmsr  ,     0x046           //       /*rmasked status register    */
.set    u_uicvr   ,     0x047           //       /*rvector register           */
.set    u_uicvcr  ,     0x048           //       /*wenable config register    */

/*----------------------------------------------------------------------------+
| High speed memory controller 0 and 1.
+----------------------------------------------------------------------------*/
.set sdram1_besr   , 0x1c1               //  bus error status register   RW
.set sdram1_bear   , 0x1c2               //  bus error address register  RW
.set sdram1_br0    , 0x1c4               //  SDRAM sub-ctrl bank reg 0   RW
.set sdram1_cr0    , 0x1c5               //  SDRAM sub-ctrl ctrl reg 0   RW
.set sdram1_br1    , 0x1c7               //  SDRAM sub-ctrl bank reg 1   RW
.set sdram1_cr1    , 0x1c8               //  SDRAM sub-ctrl ctrl reg 1   RW

.set sdram0_besr   , 0x1e1               //  bus error status register   RW
.set sdram0_bear   , 0x1e2               //  bus error address register  RW
.set sdram0_br0    , 0x1e4               //  SDRAM sub-ctrl bank reg 0   RW
.set sdram0_cr0    , 0x1e5               //  SDRAM sub-ctrl ctrl reg 0   RW
.set sdram0_br1    , 0x1e7               //  SDRAM sub-ctrl bank reg 1   RW
.set sdram0_cr1    , 0x1e8               //  SDRAM sub-ctrl ctrl reg 1   RW


.set    cic0_cr     ,   0x30              //  Chip interconnect control reg
.set    cic0_vcr    ,   0x33              //  Chip interconnect video control reg
.set    cic0_sel3   ,   0x35              //  Chip interconnect select 3 reg
.set    cic0_sccr   ,   0x120             //  Chip interconnect


/* Add some Architecture specific defines 
|  These definitions change across Vesta and Pallas
|  Pallas has 16KB, Vesta has 8KB
*/
.set    DCACHE_LINE_SIZE,        0x20
.set    DCACHE_NUM_LINES,        0x100     // # of dcache congruence classes
.set    DCACHE_PPC_SET_SIZE ,    0x2000    // Dcache_size/(num of sets assoc)