📄 initbrd.s
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// openbios/arch/vulcan/redwood6/initbrd.s, stbbios//------------------------------------------------------------------------------+//// This source code has been made available to you by IBM on an AS-IS// basis. Anyone receiving this source is licensed under IBM// copyrights to use it in any way he or she deems fit, including// copying it, modifying it, compiling it, and redistributing it either// with or without modifications. No license under IBM patents or// patent applications is to be implied by the copyright license.//// Any user of this software should understand that IBM cannot provide// technical support for this software and will not be responsible for// any consequences resulting from the use of this software.//// Any person who transfers this source code or any derivative work// must include the IBM copyright notice, this paragraph, and the// preceding two paragraphs in the transferred software.//// COPYRIGHT I B M CORPORATION 1995// LICENSED MATERIAL - PROGRAM PROPERTY OF I B M//-------------------------------------------------------------------------------//// File Name: initbrd.s//// Function: This is the architecture dependent init code for the ROM Monitor// shipped with the IBM REDWOOD5 / STB04xxx (Pallas).//// Author: Bill DeStein (initially)//// Change Activity-//// Date Description of Change BY// --------- --------------------- ---// 18-Mar-98 Ported to Redwood from Hawthorne pag// 25-Mar-98 bumped level for dccr fix pag// 26-Mar-98 bumped level for initializing sdram pag// 09-Apr-98 Fixed interrupt handling problem pag// 14-Jan-99 Porting to Redwood III pag// 31-Mar-99 Fixed code bug in data_ramc using r0 to move r3->r4 pag// 02-Apr-99 Changed code to support RIT-B & RIT-A (serial clock) pag// 02-Feb-00 Ported to Redwood IV Vesta STB jfh// 30-Dec-01 Splitted to architecture depdendent part from entry.s YYD// 26-Apr-02 Updated for Vulcan/redwood6 VK//-------------------------------------------------------------------------------// Tristate for other masters, diable ready time outs// xor r0, r0, r0 oris r1, r0,0x8000 mtdcr biucr, r1//// Set up default chip interconnect// lis r3,0xC94B ori r3,r3,0xEDEE// mtdcr cic0_sccr,r3 addis r0,r0,0x1080 ori r0,r0,0x0000 /*LP default :0003/CS2\CS3*/ mtdcr cic0_cr,r0 addi r0,r0,0x0000 mtdcr cic0_sel3,r0 addis r0,r0,0x004A ori r0,r0,0x0000 mtdcr cic0_vcr,r0//Initialize the Cross-bar switch addis r1,r0,0x0000 ori r1,r1,0x0002 mtdcr cbscr,r1//Set the hidden dcr addis r1,r0,0x4000 ori r1,r1,0x2000 mtdcr dcr_34,r1// Initialize Bank 0 for 8 bit BOOTROM Flash// xor r0, r0, r0 // mtdcr brh0, r0 // Set Bus Region Config Hi reg 0 addis r1, 0, 0x0001 ori r1, r1, 0x8000 mfdcr r0, br0 // Get current bank reg 0 settings and r0, r0, r1 // Leave on only the bus width bits oris r0, r0,0xF098 // 1 MB of flash r/w 0xFFFxxxxx-0xFFFFFFFF ori r0, r0,0x870E // 16-bit, 8-bit earlier, ready disabled mtdcr br0, r0 // Set Bus Region Config reg 0//// Initialize Bank 1 for FLASH1 only// addis r0, r0, 0x0000 mtdcr brh1, r0 // ready sampling disabled addis r0, r0,0xe078 // 8 MB of space.r/w, 0xFF0xxxxx-0xFF7xxxxx lp 2005-6-20 10:33上午 ori r0, r0,0x870E // 8-bit, ready enabled mtdcr br1, r0 // Set Bus Region Config reg 2////Initialize bank 2 for FLASH2// // addis r0, r0, 0x0000// mtdcr brh2, r0 // ready sampling enabled // addis r0, r0, 0xe878 // 4 MB of space.r/w, 0xFF8xxxxx-0xFFbxxxxx// ori r0, r0, 0x070E // 8-bit, ready enabled. // mtdcr br2, r0 // set brcr2.//Initialize bank 3 for USB// addis r0, r0, 0x0000 mtdcr brh3, r0 // ready sampling enabled addis r0, r0, 0x307C // 4 MB of space.r/w, 0xF30xxxxx-0xF38xxxxx ori r0, r0, 0x50BE // 8-bit, ready disabled. mtdcr br3, r0 // set brcr3.//// Initialize Bank 4 for Ethernet// addis r0, r0, 0x4000 mtdcr brh4, r0 // ready sampling enabled addis r0, r0,0x207C // 8 MB of space.r/w, 0xF20xxxxx-0xF28xxxxx ori r0, r0,0xD0BF // 16-bit, ready enabled mtdcr br4, r0 // Set Bus Region Config reg 2////Disable unused banks, by default they are disabled.// addis r6, r0,0xFF00 ori r6, r6,0xBFFF xor r0, r0, r0 mtdcr brh2, r0 mtdcr br2, r6 mtdcr brh5, r0 mtdcr br5, r6 mtdcr brh6, r0 mtdcr br6, r6 mtdcr brh7, r0 mtdcr br7, r6//-----------------------------------------------------------------------// Invalidate i-cache and d-cache TAG arrays.//----------------------------------------------------------------------- addi r7, r0,256 // set r7 to # of lines in data cache // for loop count- romeo has 64 lines..dcache: addi r6,0,0x0000 // clear GPR 6 mtctr r7 // set loop ctr..dcloop: dccci 0, r6 // invalidate line addi r6, r6,0x20 // bump to next line bdnz ..dcloop..icache: addi r6,0,0x0000 // clear GPR 6 iccci 0, r6 // invalidates all i-cache//-----------------------------------------------------------------------// Initialize GPIOs to minimum options needed for OpenBIOS//----------------------------------------------------------------------- addis r4,r0,0x4006 // GPIO 0 addi r0,r0,0x0 stw r0,0x0000(r4) stw r0,0x0004(r4) /* addis r0,r0,0x0000 ori r0,r0,0x0006 stw r0,0x0004(r4)*/ addis r0,r0,0x0440 ori r0,r0,0x0548 stw r0,0x0008(r4) addis r0,r0,0x4190 ori r0,r0,0x5705 stw r0,0x000c(r4) addis r0,r0,0x0440 ori r0,r0,0x0548 stw r0,0x0010(r4) addis r0,r0,0x4190 ori r0,r0,0x5705 stw r0,0x0014(r4) addis r0,r0,0x0000 ori r0,r0,0x0004 stw r0,0x0018(r4) addis r0,r0,0x0010 ori r0,r0,0x0000 stw r0,0x0030(r4) addis r0,r0,0x1405 ori r0,r0,0x0000 stw r0,0x0034(r4) addis r0,r0,0x0000 ori r0,r0,0x0011 stw r0,0x0038(r4) addis r0,r0,0x0000 ori r0,r0,0x0000 stw r0,0x003C(r4) addis r0,r0,0x0005 ori r0,r0,0x0000 stw r0,0x0040(r4) addis r0,r0,0x0000 ori r0,r0,0x0000 stw r0,0x0044(r4) addis r0,r0,0x0000 ori r0,r0,0x000c stw r0,0x0000(r4)/*-------------------------------------------------------------------------+| CONFIGURE THE HSMC CONTROLLERS| Double map HSMC into 0x00000000/0x80000000 0x20000000/0xA0000000+-------------------------------------------------------------------------*/ /* * SDRAM0 */ addis r3,0,0x0000 addis r4,0,0x0200 addis r5,0,0x2000 addis r6,0,0x2200 addis r7,0,0x81f0 addis r8,0,0x8070 /* lp add */ addis r9,0,0x80f0 addis r0,0,0 mtdcr sdram0_besr,r0 /* reset/unlock besr */ ori r0,r3,0x4010 mtdcr sdram0_br0,r0 ori r0,r4,0x3010 mtdcr sdram0_br1,r0 mtdcr sdram0_cr0,r7 mtdcr sdram0_cr1,r9 ori r0,r7,0x8000 /* enable sdram controllor */ mtdcr sdram0_cr0,r0 //ori r0,r7,0x8000 /* enable sdram controllor */ // mtdcr sdram0_cr1,r0 /* * SDRAM1 */ addis r0,0,0 mtdcr sdram1_besr,r0 /* reset/unlock besr */ ori r0,r5,0x2010 mtdcr sdram1_br0,r0 ori r0,r6,0x2010 mtdcr sdram1_br1,r0 mtdcr sdram1_cr0,r8 mtdcr sdram1_cr1,r8 ori r0,r8,0x8000 mtdcr sdram1_cr0,r0//-----------------------------------------------------------------------// A few important regs first, segmet guard, d-cache write through//----------------------------------------------------------------------- addi r0,0,0 mtsgr r0 mtdcwr r0//-----------------------------------------------------------------------// Set up some machine state registers.//----------------------------------------------------------------------- addi r4, r0,0x0000 // initialize r4 to zero mtspr esr, r4 // clear Exception Syndrome Reg mttcr r4 // timer control register addis r4, r0,0xFFFF // set r4 to 0xFFFFFFFF (status in the ori r4, r4,0xFFFF // dbsr is cleared by setting bits to 1) mtdbsr r4 // clear/reset the dbsr mtdcr besr, r4 // clear Bus Error Syndrome Reg//-----------------------------------------------------------------------// Clear reservation bit.//----------------------------------------------------------------------- addis r10, r0,0x0000 lwarx r3, r10, r10 // get some data/set resv bit stwcx. r3, r10, r10 // store out and clear resv bit//-----------------------------------------------------------------------// Clear XER.//----------------------------------------------------------------------- addis r0, r0,0x0000 mtxer r0//-----------------------------------------------------------------------// Mask off all interrupts in the universal interrupt controller//----------------------------------------------------------------------- addis r1, r0,0xFFFF ori r1, r1,0xFFFF mtdcr u_uicsr, r1 addi r0,0,0 mtdcr u_uicer, r0 addis r1, r0,0x0000 ori r1, r1,0x0000 mtdcr u_uictr, r1 addis r1, r0,0xFFFF ori r1, r1,0x8F80 mtdcr u_uicpr, r1 addis r0,0,0 mtdcr sdram1_besr,r0 /* reset/unlock besr */ ori r0,r5,0x2010 mtdcr sdram1_br0,r0 ori r0,r6,0x2010 mtdcr sdram1_br1,r0 mtdcr sdram1_cr0,r8 mtdcr sdram1_cr1,r8 ori r0,r8,0x8000 mtdcr sdram1_cr0,r0//-----------------------------------------------------------------------// A few important regs first, segmet guard, d-cache write through//----------------------------------------------------------------------- addi r0,0,0 mtsgr r0 mtdcwr r0//-----------------------------------------------------------------------// Set up some machine state registers.//----------------------------------------------------------------------- addi r4, r0,0x0000 // initialize r4 to zero mtspr esr, r4 // clear Exception Syndrome Reg mttcr r4 // timer control register addis r4, r0,0xFFFF // set r4 to 0xFFFFFFFF (status in the ori r4, r4,0xFFFF // dbsr is cleared by setting bits to 1) mtdbsr r4 // clear/reset the dbsr mtdcr besr, r4 // clear Bus Error Syndrome Reg//-----------------------------------------------------------------------// Clear reservation bit.//----------------------------------------------------------------------- addis r10, r0,0x0000 lwarx r3, r10, r10 // get some data/set resv bit stwcx. r3, r10, r10 // store out and clear resv bit//-----------------------------------------------------------------------// Clear XER.//----------------------------------------------------------------------- addis r0, r0,0x0000 mtxer r0//-----------------------------------------------------------------------// Mask off all interrupts in the universal interrupt controller//----------------------------------------------------------------------- addis r1, r0,0xFFFF ori r1, r1,0xFFFF mtdcr u_uicsr, r1 addi r0,0,0 mtdcr u_uicer, r0 addis r1, r0,0x0000 ori r1, r1,0x0000 mtdcr u_uictr, r1 addis r1, r0,0xFFFF ori r1, r1,0x8F80 mtdcr u_uicpr, r1 addis r4, r0,0xFFFF //r4 to 0xFFFFFFFF (status in the ori r4, r4,0xFFFF // dbsr is cleared by setting bits to 1) mtdbsr r4 // clear/reset the dbsr mtdcr besr, r4 // clear Bus Error Syndrome Reg//-----------------------------------------------------------------------// Clear reservation bit.//----------------------------------------------------------------------- addis r10, r0,0x0000 lwarx r3, r10, r10 // get some data/set resv bit stwcx. r3, r10, r10 // store out and clear resv bit//-----------------------------------------------------------------------// Clear XER.//----------------------------------------------------------------------- addis r0, r0,0x0000 mtxer r0//-----------------------------------------------------------------------// Mask off all interrupts in the universal interrupt controller//----------------------------------------------------------------------- addis r1, r0,0xFFFF ori r1, r1,0xFFFF mtdcr u_uicsr, r1 addi r0,0,0 mtdcr u_uicer, r0 addis r1, r0,0x0000 ori r1, r1,0x0000 mtdcr u_uictr, r1 addis r1, r0,0xFFFF ori r1, r1,0x8F80 mtdcr u_uicpr, r1⌨️ 快捷键说明
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