📄 main.dbg
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mMMDRR_MMRD7: equ %10000000
;*** BSR - Break Status Register; 0x0000FE00 ***
BSR: equ $0000FE00 ;*** BSR - Break Status Register; 0x0000FE00 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
BSR_SBSW: equ 1 ; SIM Break Stop/Wait
; bit position masks
mBSR_SBSW: equ %00000010
;*** RSR - Reset Status Register; 0x0000FE01 ***
RSR: equ $0000FE01 ;*** RSR - Reset Status Register; 0x0000FE01 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
RSR_LVI: equ 1 ; Low-Voltage Inhibit Reset Bit
RSR_MODRST: equ 2 ; Monitor Mode Entry Module Reset Bit
RSR_ILAD: equ 3 ; Illegal Address Reset Bit
RSR_ILOP: equ 4 ; Illegal Opcode Reset Bit
RSR_COP: equ 5 ; Computer Operating Properly Reset Bit
RSR_PIN: equ 6 ; External Reset Bit
RSR_POR: equ 7 ; Power-On Reset Bit
; bit position masks
mRSR_LVI: equ %00000010
mRSR_MODRST: equ %00000100
mRSR_ILAD: equ %00001000
mRSR_ILOP: equ %00010000
mRSR_COP: equ %00100000
mRSR_PIN: equ %01000000
mRSR_POR: equ %10000000
;*** BFCR - Break Flag Control Register; 0x0000FE03 ***
BFCR: equ $0000FE03 ;*** BFCR - Break Flag Control Register; 0x0000FE03 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
BFCR_BCFE: equ 7 ; Break Clear Flag Enable Bit
; bit position masks
mBFCR_BCFE: equ %10000000
;*** INT1 - Interrupt Status Register 1; 0x0000FE04 ***
INT1: equ $0000FE04 ;*** INT1 - Interrupt Status Register 1; 0x0000FE04 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
INT1_IF1: equ 2 ; Interrupt Flag 1
INT1_IF3: equ 4 ; Interrupt Flag 3
INT1_IF4: equ 5 ; Interrupt Flag 4
INT1_IF5: equ 6 ; Interrupt Flag 5
INT1_IF6: equ 7 ; Interrupt Flag 6
; bit position masks
mINT1_IF1: equ %00000100
mINT1_IF3: equ %00010000
mINT1_IF4: equ %00100000
mINT1_IF5: equ %01000000
mINT1_IF6: equ %10000000
;*** INT2 - Interrupt Status Register 2; 0x0000FE05 ***
INT2: equ $0000FE05 ;*** INT2 - Interrupt Status Register 2; 0x0000FE05 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
INT2_IF7: equ 0 ; Interrupt Flag 7
INT2_IF8: equ 1 ; Interrupt Flag 8
INT2_IF10: equ 3 ; Interrupt Flag 10
INT2_IF11: equ 4 ; Interrupt Flag 11
INT2_IF12: equ 5 ; Interrupt Flag 12
INT2_IF13: equ 6 ; Interrupt Flag 13
INT2_IF14: equ 7 ; Interrupt Flag 14
; bit position masks
mINT2_IF7: equ %00000001
mINT2_IF8: equ %00000010
mINT2_IF10: equ %00001000
mINT2_IF11: equ %00010000
mINT2_IF12: equ %00100000
mINT2_IF13: equ %01000000
mINT2_IF14: equ %10000000
;*** INT3 - Interrupt Status Register 3; 0x0000FE06 ***
INT3: equ $0000FE06 ;*** INT3 - Interrupt Status Register 3; 0x0000FE06 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
INT3_IF15: equ 0 ; Interrupt Flag 15
; bit position masks
mINT3_IF15: equ %00000001
;*** FLCR - FLASH Control Register; 0x0000FE08 ***
FLCR: equ $0000FE08 ;*** FLCR - FLASH Control Register; 0x0000FE08 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
FLCR_PGM: equ 0 ; Program Control Bit
FLCR_ERASE: equ 1 ; Erase Control Bit
FLCR_MASS: equ 2 ; Mass Erase Control Bit
FLCR_HVEN: equ 3 ; High-Voltage Enable Bit
; bit position masks
mFLCR_PGM: equ %00000001
mFLCR_ERASE: equ %00000010
mFLCR_MASS: equ %00000100
mFLCR_HVEN: equ %00001000
;*** BRK - Break Address Register; 0x0000FE0C ***
BRK: equ $0000FE0C ;*** BRK - Break Address Register; 0x0000FE0C ***
;*** BRKH - Break Address Register High; 0x0000FE0C ***
BRKH: equ $0000FE0C ;*** BRKH - Break Address Register High; 0x0000FE0C ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
BRKH_BIT8: equ 0 ; Break Address Register Bit 8
BRKH_BIT9: equ 1 ; Break Address Register Bit 9
BRKH_BIT10: equ 2 ; Break Address Register Bit 10
BRKH_BIT11: equ 3 ; Break Address Register Bit 11
BRKH_BIT12: equ 4 ; Break Address Register Bit 12
BRKH_BIT13: equ 5 ; Break Address Register Bit 13
BRKH_BIT14: equ 6 ; Break Address Register Bit 14
BRKH_BIT15: equ 7 ; Break Address Register Bit 15
; bit position masks
mBRKH_BIT8: equ %00000001
mBRKH_BIT9: equ %00000010
mBRKH_BIT10: equ %00000100
mBRKH_BIT11: equ %00001000
mBRKH_BIT12: equ %00010000
mBRKH_BIT13: equ %00100000
mBRKH_BIT14: equ %01000000
mBRKH_BIT15: equ %10000000
;*** BRKL - Break Address Register Low; 0x0000FE0D ***
BRKL: equ $0000FE0D ;*** BRKL - Break Address Register Low; 0x0000FE0D ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
BRKL_BIT0: equ 0 ; Break Address Register Bit 0
BRKL_BIT1: equ 1 ; Break Address Register Bit 1
BRKL_BIT2: equ 2 ; Break Address Register Bit 2
BRKL_BIT3: equ 3 ; Break Address Register Bit 3
BRKL_BIT4: equ 4 ; Break Address Register Bit 4
BRKL_BIT5: equ 5 ; Break Address Register Bit 5
BRKL_BIT6: equ 6 ; Break Address Register Bit 6
BRKL_BIT7: equ 7 ; Break Address Register Bit 7
; bit position masks
mBRKL_BIT0: equ %00000001
mBRKL_BIT1: equ %00000010
mBRKL_BIT2: equ %00000100
mBRKL_BIT3: equ %00001000
mBRKL_BIT4: equ %00010000
mBRKL_BIT5: equ %00100000
mBRKL_BIT6: equ %01000000
mBRKL_BIT7: equ %10000000
;*** BRKSCR - Break Status and Control Register; 0x0000FE0E ***
BRKSCR: equ $0000FE0E ;*** BRKSCR - Break Status and Control Register; 0x0000FE0E ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
BRKSCR_BRKA: equ 6 ; Break Active Bit
BRKSCR_BRKE: equ 7 ; Break Enable Bit
; bit position masks
mBRKSCR_BRKA: equ %01000000
mBRKSCR_BRKE: equ %10000000
;*** FLBPR - FLASH Block Protect Register; 0x0000FFCF ***
FLBPR: equ $0000FFCF ;*** FLBPR - FLASH Block Protect Register; 0x0000FFCF ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
FLBPR_BPR0: equ 0 ; Block Protect Register Bit 0
FLBPR_BPR1: equ 1 ; Block Protect Register Bit 1
FLBPR_BPR2: equ 2 ; Block Protect Register Bit 2
FLBPR_BPR3: equ 3 ; Block Protect Register Bit 3
FLBPR_BPR4: equ 4 ; Block Protect Register Bit 4
FLBPR_BPR5: equ 5 ; Block Protect Register Bit 5
FLBPR_BPR6: equ 6 ; Block Protect Register Bit 6
FLBPR_BPR7: equ 7 ; Block Protect Register Bit 7
; bit position masks
mFLBPR_BPR0: equ %00000001
mFLBPR_BPR1: equ %00000010
mFLBPR_BPR2: equ %00000100
mFLBPR_BPR3: equ %00001000
mFLBPR_BPR4: equ %00010000
mFLBPR_BPR5: equ %00100000
mFLBPR_BPR6: equ %01000000
mFLBPR_BPR7: equ %10000000
;*** MOR - Mask Option Register; 0x0000FFD0 ***
MOR: equ $0000FFD0 ;*** MOR - Mask Option Register; 0x0000FFD0 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
MOR_OSCSEL: equ 7 ; Oscillator Select Bit
; bit position masks
mMOR_OSCSEL: equ %10000000
;*** COPCTL - COP Control Register; 0x0000FFFF ***
COPCTL: equ $0000FFFF ;*** COPCTL - COP Control Register; 0x0000FFFF ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
COPCTL_BIT0: equ 0 ; Bit 0
COPCTL_BIT1: equ 1 ; Bit 1
COPCTL_BIT2: equ 2 ; Bit 2
COPCTL_BIT3: equ 3 ; Bit 3
COPCTL_BIT4: equ 4 ; Bit 4
COPCTL_BIT5: equ 5 ; Bit 5
COPCTL_BIT6: equ 6 ; Bit 6
COPCTL_BIT7: equ 7 ; Bit 7
; bit position masks
mCOPCTL_BIT0: equ %00000001
mCOPCTL_BIT1: equ %00000010
mCOPCTL_BIT2: equ %00000100
mCOPCTL_BIT3: equ %00001000
mCOPCTL_BIT4: equ %00010000
mCOPCTL_BIT5: equ %00100000
mCOPCTL_BIT6: equ %01000000
mCOPCTL_BIT7: equ %10000000
;***********************************************
;** D E P R E C I A T E D S Y M B O L S **
;***********************************************
IFNDEF __GENERATE_APPLICATION__ ; not supported for absolute assembler
XREF This_symb_has_been_depreciated
ENDIF
; ---------------------------------------------------------------------------
; The following symbols were removed, because they were invalid or irrelevant
; ---------------------------------------------------------------------------
; EOF
; RAM/ROM definitions
; Watchdog feed macro
feed_watchdog: MACRO
STA COPCTL ; feed the watchdog
ENDM
; variable/data section
MY_ZEROPAGE: SECTION SHORT
; Insert here your data de⌨️ 快捷键说明
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