📄 main.dbg
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;*** T2SC1 - TIM2 Channel 1 Status and Control Register; 0x00000038 ***
T2SC1: equ $00000038 ;*** T2SC1 - TIM2 Channel 1 Status and Control Register; 0x00000038 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
T2SC1_CH1MAX: equ 0 ; Channel 1 Maximum Duty Cycle Bit
T2SC1_TOV1: equ 1 ; Toggle-On-Overflow Bit
T2SC1_ELS1A: equ 2 ; Edge/Level Select Bit A
T2SC1_ELS1B: equ 3 ; Edge/Level Select Bit B
T2SC1_MS1A: equ 4 ; Mode Select Bit A
T2SC1_CH1IE: equ 6 ; Channel 1 Interrupt Enable Bit
T2SC1_CH1F: equ 7 ; Channel 1 Flag Bit
; bit position masks
mT2SC1_CH1MAX: equ %00000001
mT2SC1_TOV1: equ %00000010
mT2SC1_ELS1A: equ %00000100
mT2SC1_ELS1B: equ %00001000
mT2SC1_MS1A: equ %00010000
mT2SC1_CH1IE: equ %01000000
mT2SC1_CH1F: equ %10000000
;*** T2CH1 - TIM2 Channel 1 Register; 0x00000039 ***
T2CH1: equ $00000039 ;*** T2CH1 - TIM2 Channel 1 Register; 0x00000039 ***
;*** T2CH1H - TIM2 Channel 1 Register High; 0x00000039 ***
T2CH1H: equ $00000039 ;*** T2CH1H - TIM2 Channel 1 Register High; 0x00000039 ***
;*** T2CH1L - TIM2 Channel 1 Register Low; 0x0000003A ***
T2CH1L: equ $0000003A ;*** T2CH1L - TIM2 Channel 1 Register Low; 0x0000003A ***
;*** ADCSC - ADC10 Status and Control Register; 0x0000003C ***
ADCSC: equ $0000003C ;*** ADCSC - ADC10 Status and Control Register; 0x0000003C ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADCSC_ADCH0: equ 0 ; ADC10 Channel Select Bit 0
ADCSC_ADCH1: equ 1 ; ADC10 Channel Select Bit 1
ADCSC_ADCH2: equ 2 ; ADC10 Channel Select Bit 2
ADCSC_ADCH3: equ 3 ; ADC10 Channel Select Bit 3
ADCSC_ADCH4: equ 4 ; ADC10 Channel Select Bit 4
ADCSC_ADCO: equ 5 ; ADC10 Continuous Conversion Bit
ADCSC_AIEN: equ 6 ; ADC10 Interrupt Enable Bit
ADCSC_COCO: equ 7 ; Conversions Complete Bit
; bit position masks
mADCSC_ADCH0: equ %00000001
mADCSC_ADCH1: equ %00000010
mADCSC_ADCH2: equ %00000100
mADCSC_ADCH3: equ %00001000
mADCSC_ADCH4: equ %00010000
mADCSC_ADCO: equ %00100000
mADCSC_AIEN: equ %01000000
mADCSC_COCO: equ %10000000
;*** ADR - ADC10 Data Register; 0x0000003D ***
ADR: equ $0000003D ;*** ADR - ADC10 Data Register; 0x0000003D ***
;*** ADRH - ADC10 Data Register High; 0x0000003D ***
ADRH: equ $0000003D ;*** ADRH - ADC10 Data Register High; 0x0000003D ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADRH_AD8: equ 0 ; ADC10 Data Bit 8
ADRH_AD9: equ 1 ; ADC10 Data Bit 9
; bit position masks
mADRH_AD8: equ %00000001
mADRH_AD9: equ %00000010
;*** ADRL - ADC10 Data Register Low; 0x0000003E ***
ADRL: equ $0000003E ;*** ADRL - ADC10 Data Register Low; 0x0000003E ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADRL_AD0: equ 0 ; ADC10 Data Bit 0
ADRL_AD1: equ 1 ; ADC10 Data Bit 1
ADRL_AD2: equ 2 ; ADC10 Data Bit 2
ADRL_AD3: equ 3 ; ADC10 Data Bit 3
ADRL_AD4: equ 4 ; ADC10 Data Bit 4
ADRL_AD5: equ 5 ; ADC10 Data Bit 5
ADRL_AD6: equ 6 ; ADC10 Data Bit 6
ADRL_AD7: equ 7 ; ADC10 Data Bit 7
; bit position masks
mADRL_AD0: equ %00000001
mADRL_AD1: equ %00000010
mADRL_AD2: equ %00000100
mADRL_AD3: equ %00001000
mADRL_AD4: equ %00010000
mADRL_AD5: equ %00100000
mADRL_AD6: equ %01000000
mADRL_AD7: equ %10000000
;*** ADCLK - ADC10 Input Clock Register; 0x0000003F ***
ADCLK: equ $0000003F ;*** ADCLK - ADC10 Input Clock Register; 0x0000003F ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADCLK_ACLKEN: equ 0 ; Asynchronous Clock Source Enable
ADCLK_ADLSMP: equ 1 ; Long Sample Time Configuration
ADCLK_MODE0: equ 2 ; 10- or 8-Bit or External-Triggered Mode Selection Bit 0
ADCLK_MODE1: equ 3 ; 10- or 8-Bit or External-Triggered Mode Selection Bit 1
ADCLK_ADICLK: equ 4 ; Input Clock Select Bit
ADCLK_ADIV0: equ 5 ; ADC10 Clock Divider Bit 0
ADCLK_ADIV1: equ 6 ; ADC10 Clock Divider Bit 1
ADCLK_ADLPC: equ 7 ; ADC10 Low-Power Configuration Bit
; bit position masks
mADCLK_ACLKEN: equ %00000001
mADCLK_ADLSMP: equ %00000010
mADCLK_MODE0: equ %00000100
mADCLK_MODE1: equ %00001000
mADCLK_ADICLK: equ %00010000
mADCLK_ADIV0: equ %00100000
mADCLK_ADIV1: equ %01000000
mADCLK_ADLPC: equ %10000000
;*** MIMCR - Multi-Master IIC Master Control Register; 0x00000040 ***
MIMCR: equ $00000040 ;*** MIMCR - Multi-Master IIC Master Control Register; 0x00000040 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
MIMCR_MMBR0: equ 0 ; Baud Rate Select Bit 0
MIMCR_MMBR1: equ 1 ; Baud Rate Select Bit 1
MIMCR_MMBR2: equ 2 ; Baud Rate Select Bit 2
MIMCR_MMRW: equ 3 ; Master Read/Write
MIMCR_MMAST: equ 4 ; Master Control Bit
MIMCR_MMBB: equ 5 ; Bus Busy Flag
MIMCR_MMNAKIF: equ 6 ; No Acknowledge Interrupt Flag
MIMCR_MMALIF: equ 7 ; Multi-Master Arbitration Lost Interrupt Flag
; bit position masks
mMIMCR_MMBR0: equ %00000001
mMIMCR_MMBR1: equ %00000010
mMIMCR_MMBR2: equ %00000100
mMIMCR_MMRW: equ %00001000
mMIMCR_MMAST: equ %00010000
mMIMCR_MMBB: equ %00100000
mMIMCR_MMNAKIF: equ %01000000
mMIMCR_MMALIF: equ %10000000
;*** MMADR - Multi-Master IIC Address Register; 0x00000041 ***
MMADR: equ $00000041 ;*** MMADR - Multi-Master IIC Address Register; 0x00000041 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
MMADR_MMEXTAD: equ 0 ; Multi-Master Expanded Address
MMADR_MMAD1: equ 1 ; Multi-Master Address Bit 1
MMADR_MMAD2: equ 2 ; Multi-Master Address Bit 2
MMADR_MMAD3: equ 3 ; Multi-Master Address Bit 3
MMADR_MMAD4: equ 4 ; Multi-Master Address Bit 4
MMADR_MMAD5: equ 5 ; Multi-Master Address Bit 5
MMADR_MMAD6: equ 6 ; Multi-Master Address Bit 6
MMADR_MMAD7: equ 7 ; Multi-Master Address Bit 7
; bit position masks
mMMADR_MMEXTAD: equ %00000001
mMMADR_MMAD1: equ %00000010
mMMADR_MMAD2: equ %00000100
mMMADR_MMAD3: equ %00001000
mMMADR_MMAD4: equ %00010000
mMMADR_MMAD5: equ %00100000
mMMADR_MMAD6: equ %01000000
mMMADR_MMAD7: equ %10000000
;*** MMCR - Multi-Master IIC Control Register; 0x00000042 ***
MMCR: equ $00000042 ;*** MMCR - Multi-Master IIC Control Register; 0x00000042 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
MMCR_REPSEN: equ 2 ; Repeated Start Enable
MMCR_MMTXAK: equ 3 ; Transmit Acknowledge Enable
MMCR_MMIEN: equ 6 ; Multi-Master IIC Interrupt Enable
MMCR_MMEN: equ 7 ; Multi-Master IIC Enable
; bit position masks
mMMCR_REPSEN: equ %00000100
mMMCR_MMTXAK: equ %00001000
mMMCR_MMIEN: equ %01000000
mMMCR_MMEN: equ %10000000
;*** MMSR - Multi-Master IIC Status Register; 0x00000043 ***
MMSR: equ $00000043 ;*** MMSR - Multi-Master IIC Status Register; 0x00000043 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
MMSR_MMRXBF: equ 0 ; Multi-Master Receive Buffer Full
MMSR_MMTXBE: equ 1 ; Multi-Master Transmit Buffer Empty
MMSR_MMRXAK: equ 3 ; Multi-Master Receive Acknowledge
MMSR_MMSRW: equ 4 ; Multi-Master Slave Read/Write
MMSR_MMATCH: equ 5 ; Multi-Master Address Match
MMSR_MMTXIF: equ 6 ; Multi-Master Transmit Interrupt Flag
MMSR_MMRXIF: equ 7 ; Multi-Master IIC Receive Interrupt Flag
; bit position masks
mMMSR_MMRXBF: equ %00000001
mMMSR_MMTXBE: equ %00000010
mMMSR_MMRXAK: equ %00001000
mMMSR_MMSRW: equ %00010000
mMMSR_MMATCH: equ %00100000
mMMSR_MMTXIF: equ %01000000
mMMSR_MMRXIF: equ %10000000
;*** MMDTR - Multi-Master IIC Data Transmit Register; 0x00000044 ***
MMDTR: equ $00000044 ;*** MMDTR - Multi-Master IIC Data Transmit Register; 0x00000044 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
MMDTR_MMTD0: equ 0 ; Data Bit 0
MMDTR_MMTD1: equ 1 ; Data Bit 1
MMDTR_MMTD2: equ 2 ; Data Bit 2
MMDTR_MMTD3: equ 3 ; Data Bit 3
MMDTR_MMTD4: equ 4 ; Data Bit 4
MMDTR_MMTD5: equ 5 ; Data Bit 5
MMDTR_MMTD6: equ 6 ; Data Bit 6
MMDTR_MMTD7: equ 7 ; Data Bit 7
; bit position masks
mMMDTR_MMTD0: equ %00000001
mMMDTR_MMTD1: equ %00000010
mMMDTR_MMTD2: equ %00000100
mMMDTR_MMTD3: equ %00001000
mMMDTR_MMTD4: equ %00010000
mMMDTR_MMTD5: equ %00100000
mMMDTR_MMTD6: equ %01000000
mMMDTR_MMTD7: equ %10000000
;*** MMDRR - Multi-Master IIC Data Receive Register; 0x00000045 ***
MMDRR: equ $00000045 ;*** MMDRR - Multi-Master IIC Data Receive Register; 0x00000045 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
MMDRR_MMRD0: equ 0 ; Data Bit 0
MMDRR_MMRD1: equ 1 ; Data Bit 1
MMDRR_MMRD2: equ 2 ; Data Bit 2
MMDRR_MMRD3: equ 3 ; Data Bit 3
MMDRR_MMRD4: equ 4 ; Data Bit 4
MMDRR_MMRD5: equ 5 ; Data Bit 5
MMDRR_MMRD6: equ 6 ; Data Bit 6
MMDRR_MMRD7: equ 7 ; Data Bit 7
; bit position masks
mMMDRR_MMRD0: equ %00000001
mMMDRR_MMRD1: equ %00000010
mMMDRR_MMRD2: equ %00000100
mMMDRR_MMRD3: equ %00001000
mMMDRR_MMRD4: equ %00010000
mMMDRR_MMRD5: equ %00100000
mMMDRR_MMRD6: equ %01000000
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