main.dbg

LED显示练习

INTSCR:             equ    $0000001D                                ;*** INTSCR - IRQ Status and Control Register; 0x0000001D ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
INTSCR_MODE:        equ    0                                         ; IRQ Edge/Level Select Bit
INTSCR_IMASK:       equ    1                                         ; IRQ Interrupt Mask Bit
INTSCR_ACK:         equ    2                                         ; IRQ Interrupt Request Acknowledge Bit
INTSCR_IRQF:        equ    3                                         ; IRQ Flag
; bit position masks
mINTSCR_MODE:       equ    %00000001
mINTSCR_IMASK:      equ    %00000010
mINTSCR_ACK:        equ    %00000100
mINTSCR_IRQF:       equ    %00001000


;*** CONFIG2 - Configuration Register 2; 0x0000001E ***
CONFIG2:            equ    $0000001E                                ;*** CONFIG2 - Configuration Register 2; 0x0000001E ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
CONFIG2_STOP_ICLKDIS: equ    0                                       ; Internal oscillator STOP mode disable bit
CONFIG2_IICSEL:     equ    1                                         ; MMIIC Pin Selection Bit
CONFIG2_LVIT0:      equ    3                                         ; Low Voltage Inhibit Trip Voltage Selection Bit 0
CONFIG2_LVIT1:      equ    4                                         ; Low Voltage Inhibit Trip Voltage Selection Bit 1
CONFIG2_IRQPUD:     equ    7                                         ; IRQ1 Pin Pull-Up Control Bit
; bit position masks
mCONFIG2_STOP_ICLKDIS: equ    %00000001
mCONFIG2_IICSEL:    equ    %00000010
mCONFIG2_LVIT0:     equ    %00001000
mCONFIG2_LVIT1:     equ    %00010000
mCONFIG2_IRQPUD:    equ    %10000000


;*** CONFIG1 - Configuration Register 1; 0x0000001F ***
CONFIG1:            equ    $0000001F                                ;*** CONFIG1 - Configuration Register 1; 0x0000001F ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
CONFIG1_COPD:       equ    0                                         ; COP Disable Bit
CONFIG1_STOP:       equ    1                                         ; STOP Instruction Enable Bit
CONFIG1_SSREC:      equ    2                                         ; Short Stop Recovery Bit
CONFIG1_LVID:       equ    4                                         ; Low Voltage Inhibit Disable Bit
CONFIG1_COPRS:      equ    7                                         ; COP Reset Period Selection Bit
; bit position masks
mCONFIG1_COPD:      equ    %00000001
mCONFIG1_STOP:      equ    %00000010
mCONFIG1_SSREC:     equ    %00000100
mCONFIG1_LVID:      equ    %00010000
mCONFIG1_COPRS:     equ    %10000000


;*** T1SC - TIM1 Status and Control Register TSC; 0x00000020 ***
T1SC:               equ    $00000020                                ;*** T1SC - TIM1 Status and Control Register TSC; 0x00000020 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
T1SC_PS0:           equ    0                                         ; Prescaler Select Bit 0
T1SC_PS1:           equ    1                                         ; Prescaler Select Bit 1
T1SC_PS2:           equ    2                                         ; Prescaler Select Bit 2
T1SC_TRST:          equ    4                                         ; TIM1 Reset Bit
T1SC_TSTOP:         equ    5                                         ; TIM1 Stop Bit
T1SC_TOIE:          equ    6                                         ; TIM1 Overflow Interrupt Enable Bit
T1SC_TOF:           equ    7                                         ; TIM1 Overflow Flag Bit
; bit position masks
mT1SC_PS0:          equ    %00000001
mT1SC_PS1:          equ    %00000010
mT1SC_PS2:          equ    %00000100
mT1SC_TRST:         equ    %00010000
mT1SC_TSTOP:        equ    %00100000
mT1SC_TOIE:         equ    %01000000
mT1SC_TOF:          equ    %10000000


;*** T1CNT - TIM1 Counter Register; 0x00000021 ***
T1CNT:              equ    $00000021                                ;*** T1CNT - TIM1 Counter Register; 0x00000021 ***


;*** T1CNTH - TIM1 Counter Register High; 0x00000021 ***
T1CNTH:             equ    $00000021                                ;*** T1CNTH - TIM1 Counter Register High; 0x00000021 ***


;*** T1CNTL - TIM1 Counter Register Low; 0x00000022 ***
T1CNTL:             equ    $00000022                                ;*** T1CNTL - TIM1 Counter Register Low; 0x00000022 ***


;*** T1MOD - TIM1 Counter Modulo Register; 0x00000023 ***
T1MOD:              equ    $00000023                                ;*** T1MOD - TIM1 Counter Modulo Register; 0x00000023 ***


;*** T1MODH - TIM1 Counter Modulo Register High; 0x00000023 ***
T1MODH:             equ    $00000023                                ;*** T1MODH - TIM1 Counter Modulo Register High; 0x00000023 ***


;*** T1MODL - TIM1 Counter Modulo Register Low; 0x00000024 ***
T1MODL:             equ    $00000024                                ;*** T1MODL - TIM1 Counter Modulo Register Low; 0x00000024 ***


;*** T1SC0 - TIM1 Channel 0 Status and Control Register; 0x00000025 ***
T1SC0:              equ    $00000025                                ;*** T1SC0 - TIM1 Channel 0 Status and Control Register; 0x00000025 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
T1SC0_CH0MAX:       equ    0                                         ; Channel 0 Maximum Duty Cycle Bit
T1SC0_TOV0:         equ    1                                         ; Toggle-On-Overflow Bit
T1SC0_ELS0A:        equ    2                                         ; Edge/Level Select Bit A
T1SC0_ELS0B:        equ    3                                         ; Edge/Level Select Bit B
T1SC0_MS0A:         equ    4                                         ; Mode Select Bit A
T1SC0_MS0B:         equ    5                                         ; Mode Select Bit B
T1SC0_CH0IE:        equ    6                                         ; Channel 0 Interrupt Enable Bit
T1SC0_CH0F:         equ    7                                         ; Channel 0 Flag Bit
; bit position masks
mT1SC0_CH0MAX:      equ    %00000001
mT1SC0_TOV0:        equ    %00000010
mT1SC0_ELS0A:       equ    %00000100
mT1SC0_ELS0B:       equ    %00001000
mT1SC0_MS0A:        equ    %00010000
mT1SC0_MS0B:        equ    %00100000
mT1SC0_CH0IE:       equ    %01000000
mT1SC0_CH0F:        equ    %10000000


;*** T1CH0 - TIM1 Channel 0 Register; 0x00000026 ***
T1CH0:              equ    $00000026                                ;*** T1CH0 - TIM1 Channel 0 Register; 0x00000026 ***


;*** T1CH0H - TIM1 Channel 0 Register High; 0x00000026 ***
T1CH0H:             equ    $00000026                                ;*** T1CH0H - TIM1 Channel 0 Register High; 0x00000026 ***


;*** T1CH0L - TIM1 Channel 0 Register Low; 0x00000027 ***
T1CH0L:             equ    $00000027                                ;*** T1CH0L - TIM1 Channel 0 Register Low; 0x00000027 ***


;*** T1SC1 - TIM1 Channel 1 Status and Control Register; 0x00000028 ***
T1SC1:              equ    $00000028                                ;*** T1SC1 - TIM1 Channel 1 Status and Control Register; 0x00000028 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
T1SC1_CH1MAX:       equ    0                                         ; Channel 1 Maximum Duty Cycle Bit
T1SC1_TOV1:         equ    1                                         ; Toggle-On-Overflow Bit
T1SC1_ELS1A:        equ    2                                         ; Edge/Level Select Bit A
T1SC1_ELS1B:        equ    3                                         ; Edge/Level Select Bit B
T1SC1_MS1A:         equ    4                                         ; Mode Select Bit A
T1SC1_CH1IE:        equ    6                                         ; Channel 1 Interrupt Enable Bit
T1SC1_CH1F:         equ    7                                         ; Channel 1 Flag Bit
; bit position masks
mT1SC1_CH1MAX:      equ    %00000001
mT1SC1_TOV1:        equ    %00000010
mT1SC1_ELS1A:       equ    %00000100
mT1SC1_ELS1B:       equ    %00001000
mT1SC1_MS1A:        equ    %00010000
mT1SC1_CH1IE:       equ    %01000000
mT1SC1_CH1F:        equ    %10000000


;*** T1CH1 - TIM1 Channel 1 Register; 0x00000029 ***
T1CH1:              equ    $00000029                                ;*** T1CH1 - TIM1 Channel 1 Register; 0x00000029 ***


;*** T1CH1H - TIM1 Channel 1 Register High; 0x00000029 ***
T1CH1H:             equ    $00000029                                ;*** T1CH1H - TIM1 Channel 1 Register High; 0x00000029 ***


;*** T1CH1L - TIM1 Channel 1 Register Low; 0x0000002A ***
T1CH1L:             equ    $0000002A                                ;*** T1CH1L - TIM1 Channel 1 Register Low; 0x0000002A ***


;*** T2SC - TIM2 Status and Control Register; 0x00000030 ***
T2SC:               equ    $00000030                                ;*** T2SC - TIM2 Status and Control Register; 0x00000030 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
T2SC_PS0:           equ    0                                         ; Prescaler Select Bit 0
T2SC_PS1:           equ    1                                         ; Prescaler Select Bit 1
T2SC_PS2:           equ    2                                         ; Prescaler Select Bit 2
T2SC_TRST:          equ    4                                         ; TIM2 Reset Bit
T2SC_TSTOP:         equ    5                                         ; TIM2 Stop Bit
T2SC_TOIE:          equ    6                                         ; TIM2 Overflow Interrupt Enable Bit
T2SC_TOF:           equ    7                                         ; TIM2 Overflow Flag Bit
; bit position masks
mT2SC_PS0:          equ    %00000001
mT2SC_PS1:          equ    %00000010
mT2SC_PS2:          equ    %00000100
mT2SC_TRST:         equ    %00010000
mT2SC_TSTOP:        equ    %00100000
mT2SC_TOIE:         equ    %01000000
mT2SC_TOF:          equ    %10000000


;*** T2CNT - TIM2 Counter Register; 0x00000031 ***
T2CNT:              equ    $00000031                                ;*** T2CNT - TIM2 Counter Register; 0x00000031 ***


;*** T2CNTH - TIM2 Counter Register High; 0x00000031 ***
T2CNTH:             equ    $00000031                                ;*** T2CNTH - TIM2 Counter Register High; 0x00000031 ***


;*** T2CNTL - TIM2 Counter Register Low; 0x00000032 ***
T2CNTL:             equ    $00000032                                ;*** T2CNTL - TIM2 Counter Register Low; 0x00000032 ***


;*** T2MOD - TIM2 Counter Modulo Register; 0x00000033 ***
T2MOD:              equ    $00000033                                ;*** T2MOD - TIM2 Counter Modulo Register; 0x00000033 ***


;*** T2MODH - TIM2 Counter Modulo Register High; 0x00000033 ***
T2MODH:             equ    $00000033                                ;*** T2MODH - TIM2 Counter Modulo Register High; 0x00000033 ***


;*** T2MODL - TIM2 Counter Modulo Register Low; 0x00000034 ***
T2MODL:             equ    $00000034                                ;*** T2MODL - TIM2 Counter Modulo Register Low; 0x00000034 ***


;*** T2SC0 - TIM2 Channel 0 Status and Control Register; 0x00000035 ***
T2SC0:              equ    $00000035                                ;*** T2SC0 - TIM2 Channel 0 Status and Control Register; 0x00000035 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
T2SC0_CH0MAX:       equ    0                                         ; Channel 0 Maximum Duty Cycle Bit
T2SC0_TOV0:         equ    1                                         ; Toggle-On-Overflow Bit
T2SC0_ELS0A:        equ    2                                         ; Edge/Level Select Bit A
T2SC0_ELS0B:        equ    3                                         ; Edge/Level Select Bit B
T2SC0_MS0A:         equ    4                                         ; Mode Select Bit A
T2SC0_MS0B:         equ    5                                         ; Mode Select Bit B
T2SC0_CH0IE:        equ    6                                         ; Channel 0 Interrupt Enable Bit
T2SC0_CH0F:         equ    7                                         ; Channel 0 Flag Bit
; bit position masks
mT2SC0_CH0MAX:      equ    %00000001
mT2SC0_TOV0:        equ    %00000010
mT2SC0_ELS0A:       equ    %00000100
mT2SC0_ELS0B:       equ    %00001000
mT2SC0_MS0A:        equ    %00010000
mT2SC0_MS0B:        equ    %00100000
mT2SC0_CH0IE:       equ    %01000000
mT2SC0_CH0F:        equ    %10000000


;*** T2CH0 - TIM2 Channel 0 Register; 0x00000036 ***
T2CH0:              equ    $00000036                                ;*** T2CH0 - TIM2 Channel 0 Register; 0x00000036 ***


;*** T2CH0H - TIM2 Channel 0 Register High; 0x00000036 ***
T2CH0H:             equ    $00000036                                ;*** T2CH0H - TIM2 Channel 0 Register High; 0x00000036 ***


;*** T2CH0L - TIM2 Channel 0 Register Low; 0x00000037 ***
T2CH0L:             equ    $00000037                                ;*** T2CH0L - TIM2 Channel 0 Register Low; 0x00000037 ***