pwm.v

来自「我上传了一个pwm控制算法的代码」· Verilog 代码 · 共 39 行

module pwm (clk4,inpwm,clk_odd,pwm_out,wr_pwm);
  input        clk4;
  input[15:0]  inpwm;
  input wr_pwm;
  output       clk_odd;
  output       pwm_out;
  reg          clk_odd;
  reg[11:0]    count_p;
  reg [15:0]   pulse_width;
  reg          p;
  reg [9:0]   counter;
  parameter   N=400;

 
always @ (posedge clk4)
   if(count_p<N/2-1)        
       count_p <=count_p+ 1;
   else
       begin
      count_p<=0;
      clk_odd<=~clk_odd;
      end
always@( posedge wr_pwm) pulse_width=inpwm;//+10'b100000000; 
always @ (posedge clk4)
   if(counter<N-1)
      counter<=counter+1;      
   else
      counter<=0;
always @ (posedge clk4) 
  if(counter<pulse_width)
     p<=1;
  else 
    //if(counter==pulse_width)
    p<=0;
assign pwm_out=p;
endmodule