📄 smsc9118.c
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#define E2P_CMD_EPC_CMD_WRAL_ (0x40000000UL) // R/W
#define E2P_CMD_EPC_CMD_ERASE_ (0x50000000UL) // R/W
#define E2P_CMD_EPC_CMD_ERAL_ (0x60000000UL) // R/W
#define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000UL) // R/W
#define E2P_CMD_EPC_TIMEOUT_ (0x00000200UL) // R
#define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100UL) // RO
#define E2P_CMD_EPC_ADDR_ (0x000000FFUL) // R/W
#define E2P_DATA (0xB4UL)
#define E2P_DATA_EEPROM_DATA_ (0x000000FFUL) // R/W
//end of lan register offsets and bit definitions
#define LAN_REGISTER_EXTENT (0x00002000UL)
//The following describes the synchronization policies used in this driver.
//Register Name Policy
//RX_DATA_FIFO Only used by the Rx Thread, Rx_ProcessPackets
//TX_DATA_FIFO Only used by the Tx Thread, Tx_SendSkb
//RX_STATUS_FIFO Only used by the Rx Thread, Rx_ProcessPackets
//RX_STATUS_FIFO_PEEK Not used.
//TX_STATUS_FIFO Used in Tx_CompleteTx in Tx_UpdateTxCounters.
// protected by TxCounterLock
//TX_STATUS_FIFO_PEEK Not used.
//ID_REV Read only
//INT_CFG Set in Lan_Initialize,
// protected by IntEnableLock
//INT_STS Sharable,
//INT_EN Initialized at startup,
// Used in Rx_ProcessPackets
// otherwise protected by IntEnableLock
//BYTE_TEST Read Only
//FIFO_INT Initialized at startup,
// During run time only accessed by
// Tx_HandleInterrupt, and Tx_SendSkb and done in a safe manner
//RX_CFG Used during initialization
// During runtime only used by Rx Thread
//TX_CFG Only used during initialization
//HW_CFG Only used during initialization
//RX_DP_CTRL Only used in Rx Thread, in Rx_FastForward
//RX_FIFO_INF Read Only, Only used in Rx Thread, in Rx_PopRxStatus
//TX_FIFO_INF Read Only, Only used in Tx Thread, in Tx_GetTxStatusCount, Tx_SendSkb, Tx_CompleteTx
//PMT_CTRL Not Used
//GPIO_CFG used during initialization, in Lan_Initialize
// used for debugging
// used during EEPROM access.
// safe enough to not require a lock
//GPT_CFG protected by GpTimerLock
//GPT_CNT Not Used
//ENDIAN Not Used
//FREE_RUN Read only
//RX_DROP Used in Rx Interrupt Handler,
// and get_stats.
// safe enough to not require a lock.
//MAC_CSR_CMD Protected by MacPhyLock
//MAC_CSR_DATA Protected by MacPhyLock
// Because the two previous MAC_CSR_ registers are protected
// All MAC, and PHY registers are protected as well.
//AFC_CFG Used during initialization, in Lan_Initialize
// During run time, used in timer call back, in Phy_UpdateLinkMode
//E2P_CMD Used during initialization, in Lan_Initialize
// Used in EEPROM functions
//E2P_DATA Used in EEPROM functions
//DMA Transfer structure
typedef struct _DMA_XFER
{
DWORD dwLanReg;
DWORD *pdwBuf;
DWORD dwDmaCh;
DWORD dwDwCnt;
BOOLEAN fMemWr;
} DMA_XFER;
typedef struct _FLOW_CONTROL_PARAMETERS
{
DWORD MaxThroughput;
DWORD MaxPacketCount;
DWORD PacketCost;
DWORD BurstPeriod;
DWORD IntDeas;
} FLOW_CONTROL_PARAMETERS, *PFLOW_CONTROL_PARAMETERS;
#include PLATFORM_SOURCE
//PLATFORM_SOURCE is defined from the command line
// with the -D option
// example: -D"PLATFORM_SOURCE=\"platform.c\""
#define Lan_GetRegDW(dwOffset) \
Platform_GetRegDW(privateData->dwLanBase,dwOffset)
#define Lan_SetRegDW(dwOffset,dwVal) \
Platform_SetRegDW(privateData->dwLanBase,dwOffset,dwVal)
#define Lan_ClrBitsDW(dwOffset,dwBits) \
Platform_SetRegDW(privateData->dwLanBase, \
dwOffset,Platform_GetRegDW(privateData->dwLanBase, \
dwOffset)&(~dwBits))
#define Lan_SetBitsDW(dwOffset,dwBits) \
Platform_SetRegDW(privateData->dwLanBase, \
dwOffset,Platform_GetRegDW(privateData->dwLanBase, \
dwOffset)|dwBits);
#define LINK_OFF (0x00UL)
#define LINK_SPEED_10HD (0x01UL)
#define LINK_SPEED_10FD (0x02UL)
#define LINK_SPEED_100HD (0x04UL)
#define LINK_SPEED_100FD (0x08UL)
#define LINK_SYMMETRIC_PAUSE (0x10UL)
#define LINK_ASYMMETRIC_PAUSE (0x20UL)
#define LINK_AUTO_NEGOTIATE (0x40UL)
typedef unsigned long VL_KEY;
typedef struct _VERIFIABLE_LOCK {
spinlock_t Lock;
VL_KEY KeyCode;
} VERIFIABLE_LOCK, * PVERIFIABLE_LOCK;
void Vl_InitLock(PVERIFIABLE_LOCK pVl);
BOOLEAN Vl_CheckLock(PVERIFIABLE_LOCK pVl,VL_KEY keyCode);
VL_KEY Vl_WaitForLock(PVERIFIABLE_LOCK pVl,DWORD *pdwIntFlags);
void Vl_ReleaseLock(PVERIFIABLE_LOCK pVl,VL_KEY keyCode,DWORD *pdwIntFlags);
typedef struct _PRIVATE_DATA {
DWORD dwLanBase;
DWORD dwIdRev;
DWORD dwFpgaRev;
struct net_device *dev;
DWORD dwGeneration;//used to decide which workarounds apply
spinlock_t IntEnableLock;
BOOLEAN LanInitialized;
VERIFIABLE_LOCK MacPhyLock;
DWORD dwTxDmaCh;
BOOLEAN TxDmaChReserved;
DMA_XFER TxDmaXfer;
DWORD dwTxDmaThreshold;
DWORD dwTxQueueDisableMask;
struct sk_buff *TxSkb;
spinlock_t TxSkbLock;
spinlock_t TxQueueLock;
spinlock_t TxCounterLock;
BOOLEAN TxInitialized;
DWORD dwRxDmaCh;
struct sk_buff *RxSkb;
BOOLEAN RxDmaChReserved;
DWORD dwRxDmaThreshold;
BOOLEAN RxCongested;
DWORD dwRxOffCount;
BOOLEAN RxOverrun;
DWORD RxOverrunCount;
DWORD RxStatusDWReadCount;
DWORD RxDataDWReadCount;
DWORD RxPacketReadCount;
DWORD RxFastForwardCount;
DWORD RxPioReadCount;
DWORD RxDmaReadCount;
DWORD RxCongestedCount;
DWORD RxDumpCount;
DWORD LastReasonForReleasingCPU;
DWORD LastRxStatus1;
DWORD LastRxStatus2;
DWORD LastRxStatus3;
DWORD LastIntStatus1;
DWORD LastIntStatus2;
DWORD LastIntStatus3;
DWORD RxUnloadProgress;
DWORD RxUnloadPacketProgress;
DWORD RxMaxDataFifoSize;
DWORD RxFlowCurrentThroughput;
DWORD RxFlowCurrentPacketCount;
DWORD RxFlowCurrentWorkLoad;
BOOLEAN MeasuringRxThroughput;
DWORD RxFlowMeasuredMaxThroughput;
DWORD RxFlowMeasuredMaxPacketCount;
//RX_FLOW_ACTIVATION specifies the percentage that RxFlowCurrentWorkLoad must exceed
// RxFlowMaxWorkLoad in order to activate flow control
#define RX_FLOW_ACTIVATION (4UL)
//RX_FLOW_DEACTIVATION specifies the percentage that RxFlowCurrentWorkLoad must reduce
// from RxFlowMaxWorkLoad in order to deactivate flow control
#define RX_FLOW_DEACTIVATION (25UL)
DWORD RxFlowMaxWorkLoad;
FLOW_CONTROL_PARAMETERS RxFlowParameters;
DWORD RxFlowBurstWorkLoad;
DWORD RxFlowBurstMaxWorkLoad;
BOOLEAN RxFlowControlActive;
BOOLEAN RxFlowBurstActive;
DWORD RxInterrupts;
#define GPT_SCHEDULE_DEPTH (3)
void *GptFunction[GPT_SCHEDULE_DEPTH];
DWORD GptCallTime[GPT_SCHEDULE_DEPTH];
DWORD Gpt_scheduled_slot_index;
spinlock_t GpTimerLock;
BOOLEAN Running;
struct net_device_stats stats;
DWORD dwPhyAddress;
DWORD dwPhyId;
#ifdef USE_LED1_WORK_AROUND
DWORD NotUsingExtPhy;
#endif
BYTE bPhyModel;
BYTE bPhyRev;
DWORD dwLinkSpeed;
DWORD dwLinkSettings;
DWORD dwRemoteFaultCount;
struct timer_list LinkPollingTimer;
BOOLEAN StopLinkPolling;
WORD wLastADV;
WORD wLastADVatRestart;
#ifdef USE_PHY_WORK_AROUND
#define MIN_PACKET_SIZE (64)
DWORD dwTxStartMargen;
BYTE LoopBackTxPacket[MIN_PACKET_SIZE];
DWORD dwTxEndMargen;
DWORD dwRxStartMargen;
BYTE LoopBackRxPacket[MIN_PACKET_SIZE];
DWORD dwRxEndMargen;
DWORD dwResetCount;
#endif
BOOLEAN SoftwareInterruptSignal;
PLATFORM_DATA PlatformData;
#define SMSC_IF_NAME_SIZE (10)
char ifName[SMSC_IF_NAME_SIZE];
/* for Rx Multicast work around */
volatile DWORD HashLo;
volatile DWORD HashHi;
volatile BOOLEAN MulticastUpdatePending;
volatile DWORD set_bits_mask;
volatile DWORD clear_bits_mask;
} PRIVATE_DATA, *PPRIVATE_DATA;
/*
****************************************************************************
****************************************************************************
* MAC Control and Status Register (Indirect Address)
* Offset (through the MAC_CSR CMD and DATA port)
****************************************************************************
****************************************************************************
*
*/
#define MAC_CR (0x01UL) // R/W
/* MAC_CR - MAC Control Register */
#define MAC_CR_RXALL_ (0x80000000UL)
#define MAC_CR_HBDIS_ (0x10000000UL)
#define MAC_CR_RCVOWN_ (0x00800000UL)
#define MAC_CR_LOOPBK_ (0x00200000UL)
#define MAC_CR_FDPX_ (0x00100000UL)
#define MAC_CR_MCPAS_ (0x00080000UL)
#define MAC_CR_PRMS_ (0x00040000UL)
#define MAC_CR_INVFILT_ (0x00020000UL)
#define MAC_CR_PASSBAD_ (0x00010000UL)
#define MAC_CR_HFILT_ (0x00008000UL)
#define MAC_CR_HPFILT_ (0x00002000UL)
#define MAC_CR_LCOLL_ (0x00001000UL)
#define MAC_CR_BCAST_ (0x00000800UL)
#define MAC_CR_DISRTY_ (0x00000400UL)
#define MAC_CR_PADSTR_ (0x00000100UL)
#define MAC_CR_BOLMT_MASK_ (0x000000C0UL)
#define MAC_CR_DFCHK_ (0x00000020UL)
#define MAC_CR_TXEN_ (0x00000008UL)
#define MAC_CR_RXEN_ (0x00000004UL)
#define ADDRH (0x02UL) // R/W mask 0x0000FFFFUL
#define ADDRL (0x03UL) // R/W mask 0xFFFFFFFFUL
#define HASHH (0x04UL) // R/W
#define HASHL (0x05UL) // R/W
#define MII_ACC (0x06UL) // R/W
#define MII_ACC_PHY_ADDR_ (0x0000F800UL)
#define MII_ACC_MIIRINDA_ (0x000007C0UL)
#define MII_ACC_MII_WRITE_ (0x00000002UL)
#define MII_ACC_MII_BUSY_ (0x00000001UL)
#define MII_DATA (0x07UL) // R/W mask 0x0000FFFFUL
#define FLOW (0x08UL) // R/W
#define FLOW_FCPT_ (0xFFFF0000UL)
#define FLOW_FCPASS_ (0x00000004UL)
#define FLOW_FCEN_ (0x00000002UL)
#define FLOW_FCBSY_ (0x00000001UL)
#define VLAN1 (0x09UL) // R/W mask 0x0000FFFFUL
#define VLAN2 (0x0AUL) // R/W mask 0x0000FFFFUL
#define WUFF (0x0BUL) // WO
#define WUCSR (0x0CUL) // R/W
#define WUCSR_GUE_ (0x00000200UL)
#define WUCSR_WUFR_ (0x00000040UL)
#define WUCSR_MPR_ (0x00000020UL)
#define WUCSR_WAKE_EN_ (0x00000004UL)
#define WUCSR_MPEN_ (0x00000002UL)
BOOLEAN Mac_Initialize(PPRIVATE_DATA privateData);
static BOOLEAN MacNotBusy(PPRIVATE_DATA privateData,VL_KEY keyCode);
DWORD Mac_GetRegDW(PPRIVATE_DATA privateData,DWORD dwRegOffset,VL_KEY keyCode);
void Mac_SetRegDW(PPRIVATE_DATA privateData,DWORD dwRegOffset,DWORD dwVal,VL_KEY keyCode);
/*
****************************************************************************
* Chip Specific MII Defines
****************************************************************************
*
* Phy register offsets and bit definitions
*
*/
#define LAN9118_PHY_ID (0x00C0001C)
#define PHY_BCR ((DWORD)0U)
#define PHY_BCR_RESET_ ((WORD)0x8000U)
#define PHY_BCR_LOOPBACK_ ((WORD)0x4000U)
#define PHY_BCR_SPEED_SELECT_ ((WORD)0x2000U)
#define PHY_BCR_AUTO_NEG_ENABLE_ ((WORD)0x1000U)
#define PHY_BCR_RESTART_AUTO_NEG_ ((WORD)0x0200U)
#define PHY_BCR_DUPLEX_MODE_ ((WORD)0x0100U)
#define PHY_BSR ((DWORD)1U)
#define PHY_BSR_LINK_STATUS_ ((WORD)0x0004U)
#define PHY_BSR_REMOTE_FAULT_ ((WORD)0x0010U)
#define PHY_BSR_AUTO_NEG_COMP_ ((WORD)0x0020U)
#define PHY_ID_1 ((DWORD)2U)
#define PHY_ID_2 ((DWORD)3U)
#define PHY_ANEG_ADV ((DWORD)4U)
#define PHY_ANEG_ADV_PAUSE_ ((WORD)0x0C00)
#define PHY_ANEG_ADV_ASYMP_ ((WORD)0x0800)
#define PHY_ANEG_ADV_SYMP_ ((WORD)0x0400)
#define PHY_ANEG_ADV_10H_ ((WORD)0x20)
#define PHY_ANEG_ADV_10F_ ((WORD)0x40)
#define PHY_ANEG_ADV_100H_ ((WORD)0x80)
#define PHY_ANEG_ADV_100F_ ((WORD)0x100)
#define PHY_ANEG_ADV_SPEED_ ((WORD)0x1E0)
#define PHY_ANEG_LPA ((DWORD)5U)
#define PHY_ANEG_LPA_ASYMP_ ((WORD)0x0800)
#define PHY_ANEG_LPA_SYMP_ ((WORD)0x0400)
#define PHY_ANEG_LPA_100FDX_ ((WORD)0x0100)
#define PHY_ANEG_LPA_100HDX_ ((WORD)0x0080)
#define PHY_ANEG_LPA_10FDX_ ((WORD)0x0040)
#define PHY_ANEG_LPA_10HDX_ ((WORD)0x0020)
#define PHY_MODE_CTRL_STS ((DWORD)17) // Mode Control/Status Register
#define MODE_CTRL_STS_FASTRIP_ ((WORD)0x4000U)
#define MODE_CTRL_STS_EDPWRDOWN_ ((WORD)0x2000U)
#define MODE_CTRL_STS_LOWSQEN_ ((WORD)0x0800U)
#define MODE_CTRL_STS_MDPREBP_ ((WORD)0x0400U)
#define MODE_CTRL_STS_FARLOOPBACK_ ((WORD)0x0200U)
#define MODE_CTRL_STS_FASTEST_ ((WORD)0x0100U)
#define MODE_CTRL_STS_REFCLKEN_ ((WORD)0x0010U)
#define MODE_CTRL_STS_PHYADBP_ ((WORD)0x0008U)
#define MODE_CTRL_STS_FORCE_G_LINK_ ((WORD)0x0004U)
#define MODE_CTRL_STS_ENERGYON_ ((WORD)0x0002U)
#define PHY_INT_SRC ((DWORD)29)
#define PHY_INT_SRC_ENERGY_ON_ ((WORD)0x0080U)
#define PHY_INT_SRC_ANEG_COMP_ ((WORD)0x0040U)
#define PHY_INT_SRC_REMOTE_FAULT_ ((WORD)0x0020U)
#define PHY_INT_SRC_LINK_DOWN_ ((WORD)0x0010U)
#define PHY_INT_MASK ((DWORD)30)
#define PHY_INT_MASK_ENERGY_ON_ ((WORD)0x0080U)
#define PHY_INT_MASK_ANEG_COMP_ ((WORD)0x0040U)
#define PHY_INT_MASK_REMOTE_FAULT_ ((WORD)0x0020U)
#define PHY_INT_MASK_LINK_DOWN_ ((WORD)0x0010U)
#define PHY_SPECIAL ((DWORD)31)
#define PHY_SPECIAL_SPD_ ((WORD)0x001CU)
#define PHY_SPECIAL_SPD_10HALF_ ((WORD)0x0004U)
#define PHY_SPECIAL_SPD_10FULL_ ((WORD)0x0014U)
#define PHY_SPECIAL_SPD_100HALF_ ((WORD)0x0008U)
#define PHY_SPECIAL_SPD_100FULL_ ((WORD)0x0018U)
BOOLEAN Phy_Initialize(
PPRIVATE_DATA privateData,
DWORD dwPhyAddress,
DWORD dwLinkMode);
void Phy_SetLink(PPRIVATE_DATA privateData,
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