bamboo.h

来自「适合KS8695X」· C头文件 代码 · 共 402 行 · 第 1/2 页

#define EBC0_BNCR_BS_4MB	0x00040000
#define EBC0_BNCR_BS_8MB	0x00060000
#define EBC0_BNCR_BS_16MB	0x00080000
#define EBC0_BNCR_BS_32MB	0x000A0000
#define EBC0_BNCR_BS_64MB	0x000C0000
#define EBC0_BNCR_BS_128MB	0x000E0000
/* BU - Bank Usage */
#define EBC0_BNCR_BU_MASK	0x00018000
#define EBC0_BNCR_BU_RO		    0x00008000
#define EBC0_BNCR_BU_WO		    0x00010000
#define EBC0_BNCR_BU_RW		0x00018000
/* BW - Bus Width */
#define EBC0_BNCR_BW_MASK	0x00006000
#define EBC0_BNCR_BW_8BIT	0x00000000
#define EBC0_BNCR_BW_16BIT	0x00002000
#define EBC0_BNCR_BW_32BIT	0x00004000

/*----------------------------------------------------------------------------+
| Peripheral Bank Access Parameters - EBC0_BnAP
+----------------------------------------------------------------------------*/
/* Burst Mode Enable */
#define EBC0_BNAP_BME_ENABLED	    0x80000000
#define EBC0_BNAP_BME_DISABLED	    0x00000000
/* Transfert Wait */
#define EBC0_BNAP_TWT_ENCODE(n)	    ((((unsigned long)(n))&0xFF)<<23)	/* Bits 1:8 */
/* Chip Select On Timing */
#define EBC0_BNAP_CSN_ENCODE(n)	    ((((unsigned long)(n))&0x3)<<18)	/* Bits 12:13 */
/* Output Enable On Timing */
#define EBC0_BNAP_OEN_ENCODE(n)	    ((((unsigned long)(n))&0x3)<<16)	/* Bits 14:15 */
/* Write Back Enable On Timing */
#define EBC0_BNAP_WBN_ENCODE(n)	    ((((unsigned long)(n))&0x3)<<14)	/* Bits 16:17 */
/* Write Back Enable Off Timing */
#define EBC0_BNAP_WBF_ENCODE(n)	    ((((unsigned long)(n))&0x3)<<12)	/* Bits 18:19 */
/* Transfert Hold */
#define EBC0_BNAP_TH_ENCODE(n)	    ((((unsigned long)(n))&0x7)<<9)	/* Bits 20:22 */
/* PerReady Enable */
#define EBC0_BNAP_RE_ENABLED	    0x00000100
#define EBC0_BNAP_RE_DISABLED	    0x00000000
/* Sample On Ready */
#define EBC0_BNAP_SOR_DELAYED	    0x00000000
#define EBC0_BNAP_SOR_NOT_DELAYED   0x00000080
/* Byte Enable Mode */
#define EBC0_BNAP_BEM_WRITEONLY	    0x00000000
#define EBC0_BNAP_BEM_RW	    0x00000040
/* Parity Enable */
#define EBC0_BNAP_PEN_DISABLED	    0x00000000
#define EBC0_BNAP_PEN_ENABLED	    0x00000020

/*----------------------------------------------------------------------------+
| Define Boot devices
+----------------------------------------------------------------------------*/
/* */
#define BOOT_FROM_SMALL_FLASH		0x00
#define BOOT_FROM_LARGE_FLASH_OR_SRAM	0x01
#define BOOT_FROM_NAND_FLASH0		0x02
#define BOOT_FROM_PCI			0x03
#define BOOT_DEVICE_UNKNOWN		0x04


#define	 PVR_POWERPC_440EP_PASS1    0x42221850
#define	 PVR_POWERPC_440EP_PASS2    0x422218D3

#define TRUE 1
#define FALSE 0

#define GPIO_GROUP_MAX	    2
#define GPIO_MAX	    32
#define GPIO_ALT1_SEL	    0x40000000	    /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
#define GPIO_ALT2_SEL	    0x80000000	    /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
#define GPIO_ALT3_SEL	    0xC0000000	    /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
#define GPIO_MASK	    0xC0000000	    /* GPIO_MASK */
#define GPIO_IN_SEL	    0x40000000	    /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
					    /* For the other GPIO number, you must shift */

#define GPIO0		0
#define GPIO1		1


/*#define MAX_SELECTION_NB	CORE_NB */
#define MAX_CORE_SELECT_NB	22

/*----------------------------------------------------------------------------+
  | PPC440EP GPIOs addresses.
  +----------------------------------------------------------------------------*/
#define GPIO0_BASE	 0xEF600B00
#define GPIO0_REAL	 0xEF600B00

#define GPIO1_BASE	 0xEF600C00
#define GPIO1_REAL	 0xEF600C00

/* Offsets */
#define GPIOx_OR    0x00	/* GPIO Output Register */
#define GPIOx_TCR   0x04	/* GPIO Three-State Control Register */
#define GPIOx_OSL   0x08	/* GPIO Output Select Register (Bits 0-31) */
#define GPIOx_OSH   0x0C	/* GPIO Ouput Select Register (Bits 32-63) */
#define GPIOx_TSL   0x10	/* GPIO Three-State Select Register (Bits 0-31) */
#define GPIOx_TSH   0x14	/* GPIO Three-State Select Register  (Bits 32-63) */
#define GPIOx_ODR   0x18	/* GPIO Open drain Register */
#define GPIOx_IR    0x1C	/* GPIO Input Register */
#define GPIOx_RR1   0x20	/* GPIO Receive Register 1 */
#define GPIOx_RR2   0x24	/* GPIO Receive Register 2 */
#define GPIOx_RR3   0x28	/* GPIO Receive Register 3 */
#define GPIOx_IS1L  0x30	/* GPIO Input Select Register 1 (Bits 0-31) */
#define GPIOx_IS1H  0x34	/* GPIO Input Select Register 1 (Bits 32-63) */
#define GPIOx_IS2L  0x38	/* GPIO Input Select Register 2 (Bits 0-31) */
#define GPIOx_IS2H  0x3C	/* GPIO Input Select Register 2 (Bits 32-63) */
#define GPIOx_IS3L  0x40	/* GPIO Input Select Register 3 (Bits 0-31) */
#define GPIOx_IS3H  0x44	/* GPIO Input Select Register 3 (Bits 32-63) */

/* GPIO0 */
#define GPIO0_IS1L	(GPIO0_BASE+GPIOx_IS1L)
#define GPIO0_IS1H	(GPIO0_BASE+GPIOx_IS1H)
#define GPIO0_IS2L	(GPIO0_BASE+GPIOx_IS2L)
#define GPIO0_IS2H	(GPIO0_BASE+GPIOx_IS2H)
#define GPIO0_IS3L	(GPIO0_BASE+GPIOx_IS3L)
#define GPIO0_IS3H	(GPIO0_BASE+GPIOx_IS3L)

/* GPIO1 */
#define GPIO1_IS1L	(GPIO1_BASE+GPIOx_IS1L)
#define GPIO1_IS1H	(GPIO1_BASE+GPIOx_IS1H)
#define GPIO1_IS2L	(GPIO1_BASE+GPIOx_IS2L)
#define GPIO1_IS2H	(GPIO1_BASE+GPIOx_IS2H)
#define GPIO1_IS3L	(GPIO1_BASE+GPIOx_IS3L)
#define GPIO1_IS3H	(GPIO1_BASE+GPIOx_IS3L)

#define GPIO_OS(x)	(x+GPIOx_OSL)	 /* GPIO Output Register High or Low */
#define GPIO_TS(x)	(x+GPIOx_TSL)	 /* GPIO Three-state Control Reg High or Low */
#define GPIO_IS1(x)	(x+GPIOx_IS1L)	 /* GPIO Input register1 High or Low */
#define GPIO_IS2(x)	(x+GPIOx_IS2L)	 /* GPIO Input register2 High or Low */
#define GPIO_IS3(x)	(x+GPIOx_IS3L)	 /* GPIO Input register3 High or Low */


/*----------------------------------------------------------------------------+
  | Declare Configuration values
  +----------------------------------------------------------------------------*/
typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;

typedef struct { unsigned long	add;	/* gpio core base address */
	gpio_driver_t  in_out; /* Driver Setting */
	gpio_select_t  alt_nb; /* Selected Alternate */
} gpio_param_s;

/*----------------------------------------------------------------------------+
  |			XX     XX
  |
  | XXXXXX   XXX XX    XXX    XXX
  |    XX    XX X XX	XX     XX
  |   XX     XX X XX	XX     XX
  |  XX	     XX	  XX	XX     XX
  | XXXXXX   XXX  XXX  XXXX   XXXX
  +----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------+
  | Defines
  +----------------------------------------------------------------------------*/
typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN,
			   ZMII_CONFIGURATION_IS_MII,
			   ZMII_CONFIGURATION_IS_RMII,
			   ZMII_CONFIGURATION_IS_SMII
} zmii_config_t;

/*----------------------------------------------------------------------------+
  | Declare Configuration values
  +----------------------------------------------------------------------------*/
typedef enum uart_config_nb { L1, L2, L3, L4 } uart_config_nb_t;
typedef enum core_selection { CORE_NOT_SELECTED, CORE_SELECTED} core_selection_t;
typedef enum config_list {  IIC_CORE,
			    SCP_CORE,
			    DMA_CHANNEL_AB,
			    UIC_4_9,
			    USB2_HOST,
			    DMA_CHANNEL_CD,
			    USB2_DEVICE,
			    PACKET_REJ_FUNC_AVAIL,
			    USB1_DEVICE,
			    EBC_MASTER,
			    NAND_FLASH,
			    UART_CORE0,
			    UART_CORE1,
			    UART_CORE2,
			    UART_CORE3,
			    MII_SEL,
			    RMII_SEL,
			    SMII_SEL,
			    PACKET_REJ_FUNC_EN,
			    UIC_0_3,
			    USB1_HOST,
			    PCI_PATCH,
			    CORE_NB
} core_list_t;

typedef enum block3_value { B3_V1,  B3_V2,  B3_V3,  B3_V4,  B3_V5,
			    B3_V6,  B3_V7,  B3_V8,  B3_V9,  B3_V10,
			    B3_V11, B3_V12, B3_V13, B3_V14, B3_V15,
			    B3_V16, B3_VALUE_UNKNOWN
} block3_value_t;

typedef enum config_validity { CONFIG_IS_VALID,
			       CONFIG_IS_INVALID
} config_validity_t;