bamboo.c
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C
1,843 行
/*
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <spd_sdram.h>
#include <ppc440.h>
#include "bamboo.h"
void ext_bus_cntlr_init(void);
void configure_ppc440ep_pins(void);
int is_nand_selected(void);
gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
#if 0
{ /* GPIO Alternate1 Alternate2 Alternate3 */
{
/* GPIO Core 0 */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */
{ GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */
{ GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */
},
{
/* GPIO Core 1 */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */
{ GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
}
};
#endif
/*----------------------------------------------------------------------------+
| EBC Devices Characteristics
| Peripheral Bank Access Parameters - EBC0_BnAP
| Peripheral Bank Configuration Register - EBC0_BnCR
+----------------------------------------------------------------------------*/
/* Small Flash */
#define EBC0_BNAP_SMALL_FLASH \
EBC0_BNAP_BME_DISABLED | \
EBC0_BNAP_TWT_ENCODE(6) | \
EBC0_BNAP_CSN_ENCODE(0) | \
EBC0_BNAP_OEN_ENCODE(1) | \
EBC0_BNAP_WBN_ENCODE(1) | \
EBC0_BNAP_WBF_ENCODE(3) | \
EBC0_BNAP_TH_ENCODE(1) | \
EBC0_BNAP_RE_ENABLED | \
EBC0_BNAP_SOR_DELAYED | \
EBC0_BNAP_BEM_WRITEONLY | \
EBC0_BNAP_PEN_DISABLED
#define EBC0_BNCR_SMALL_FLASH_CS0 \
EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
EBC0_BNCR_BS_1MB | \
EBC0_BNCR_BU_RW | \
EBC0_BNCR_BW_8BIT
#define EBC0_BNCR_SMALL_FLASH_CS4 \
EBC0_BNCR_BAS_ENCODE(0x87F00000) | \
EBC0_BNCR_BS_1MB | \
EBC0_BNCR_BU_RW | \
EBC0_BNCR_BW_8BIT
/* Large Flash or SRAM */
#define EBC0_BNAP_LARGE_FLASH_OR_SRAM \
EBC0_BNAP_BME_DISABLED | \
EBC0_BNAP_TWT_ENCODE(8) | \
EBC0_BNAP_CSN_ENCODE(0) | \
EBC0_BNAP_OEN_ENCODE(1) | \
EBC0_BNAP_WBN_ENCODE(1) | \
EBC0_BNAP_WBF_ENCODE(1) | \
EBC0_BNAP_TH_ENCODE(2) | \
EBC0_BNAP_SOR_DELAYED | \
EBC0_BNAP_BEM_RW | \
EBC0_BNAP_PEN_DISABLED
#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \
EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
EBC0_BNCR_BS_8MB | \
EBC0_BNCR_BU_RW | \
EBC0_BNCR_BW_16BIT
#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \
EBC0_BNCR_BAS_ENCODE(0x87800000) | \
EBC0_BNCR_BS_8MB | \
EBC0_BNCR_BU_RW | \
EBC0_BNCR_BW_16BIT
/* NVRAM - FPGA */
#define EBC0_BNAP_NVRAM_FPGA \
EBC0_BNAP_BME_DISABLED | \
EBC0_BNAP_TWT_ENCODE(9) | \
EBC0_BNAP_CSN_ENCODE(0) | \
EBC0_BNAP_OEN_ENCODE(1) | \
EBC0_BNAP_WBN_ENCODE(1) | \
EBC0_BNAP_WBF_ENCODE(0) | \
EBC0_BNAP_TH_ENCODE(2) | \
EBC0_BNAP_RE_ENABLED | \
EBC0_BNAP_SOR_DELAYED | \
EBC0_BNAP_BEM_WRITEONLY | \
EBC0_BNAP_PEN_DISABLED
#define EBC0_BNCR_NVRAM_FPGA_CS5 \
EBC0_BNCR_BAS_ENCODE(0x80000000) | \
EBC0_BNCR_BS_1MB | \
EBC0_BNCR_BU_RW | \
EBC0_BNCR_BW_8BIT
/* Nand Flash */
#define EBC0_BNAP_NAND_FLASH \
EBC0_BNAP_BME_DISABLED | \
EBC0_BNAP_TWT_ENCODE(3) | \
EBC0_BNAP_CSN_ENCODE(0) | \
EBC0_BNAP_OEN_ENCODE(0) | \
EBC0_BNAP_WBN_ENCODE(0) | \
EBC0_BNAP_WBF_ENCODE(0) | \
EBC0_BNAP_TH_ENCODE(1) | \
EBC0_BNAP_RE_ENABLED | \
EBC0_BNAP_SOR_NOT_DELAYED | \
EBC0_BNAP_BEM_RW | \
EBC0_BNAP_PEN_DISABLED
#define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000
/* NAND0 */
#define EBC0_BNCR_NAND_FLASH_CS1 \
EBC0_BNCR_BAS_ENCODE(0x90000000) | \
EBC0_BNCR_BS_1MB | \
EBC0_BNCR_BU_RW | \
EBC0_BNCR_BW_32BIT
/* NAND1 - Bank2 */
#define EBC0_BNCR_NAND_FLASH_CS2 \
EBC0_BNCR_BAS_ENCODE(0x94000000) | \
EBC0_BNCR_BS_1MB | \
EBC0_BNCR_BU_RW | \
EBC0_BNCR_BW_32BIT
/* NAND1 - Bank3 */
#define EBC0_BNCR_NAND_FLASH_CS3 \
EBC0_BNCR_BAS_ENCODE(0x94000000) | \
EBC0_BNCR_BS_1MB | \
EBC0_BNCR_BU_RW | \
EBC0_BNCR_BW_32BIT
int board_early_init_f(void)
{
ext_bus_cntlr_init();
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
/*--------------------------------------------------------------------
* Setup the GPIO pins
*-------------------------------------------------------------------*/
out32(GPIO0_OSRL, 0x00000400);
out32(GPIO0_OSRH, 0x00000000);
out32(GPIO0_TSRL, 0x00000400);
out32(GPIO0_TSRH, 0x00000000);
out32(GPIO0_ISR1L, 0x00000000);
out32(GPIO0_ISR1H, 0x00000000);
out32(GPIO0_ISR2L, 0x00000000);
out32(GPIO0_ISR2H, 0x00000000);
out32(GPIO0_ISR3L, 0x00000000);
out32(GPIO0_ISR3H, 0x00000000);
out32(GPIO1_OSRL, 0x0C380000);
out32(GPIO1_OSRH, 0x00000000);
out32(GPIO1_TSRL, 0x0C380000);
out32(GPIO1_TSRH, 0x00000000);
out32(GPIO1_ISR1L, 0x0FC30000);
out32(GPIO1_ISR1H, 0x00000000);
out32(GPIO1_ISR2L, 0x0C010000);
out32(GPIO1_ISR2H, 0x00000000);
out32(GPIO1_ISR3L, 0x01400000);
out32(GPIO1_ISR3H, 0x00000000);
configure_ppc440ep_pins();
return 0;
}
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
/*----------------------------------------------------------------------------+
| nand_reset.
| Reset Nand flash
| This routine will abort previous cmd
+----------------------------------------------------------------------------*/
int nand_reset(ulong addr)
{
int wait=0, stat=0;
out8(addr + NAND_CMD_REG, NAND0_CMD_RESET);
out8(addr + NAND_CMD_REG, NAND0_CMD_READ_STATUS);
while ((stat != 0xc0) && (wait != 0xffff)) {
stat = in8(addr + NAND_DATA_REG);
wait++;
}
if (stat == 0xc0) {
return 0;
} else {
printf("NAND Reset timeout.\n");
return -1;
}
}
void board_nand_set_device(int cs, ulong addr)
{
/* Set NandFlash Core Configuration Register */
out32(addr + NAND_CCR_REG, 0x00001000 | (cs << 24));
switch (cs) {
case 1:
/* -------
* NAND0
* -------
* K9F1208U0A : 4 addr cyc, 1 col + 3 Row
* Set NDF1CR - Enable External CS1 in NAND FLASH controller
*/
out32(addr + NAND_CR1_REG, 0x80002222);
break;
case 2:
/* -------
* NAND1
* -------
* K9K2G0B : 5 addr cyc, 2 col + 3 Row
* Set NDF2CR : Enable External CS2 in NAND FLASH controller
*/
out32(addr + NAND_CR2_REG, 0xC0007777);
break;
}
/* Perform Reset Command */
if (nand_reset(addr) != 0)
return;
}
void nand_init(void)
{
board_nand_set_device(1, CFG_NAND_ADDR);
nand_probe(CFG_NAND_ADDR);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
#if 0 /* NAND1 not supported yet */
board_nand_set_device(2, CFG_NAND2_ADDR);
nand_probe(CFG_NAND2_ADDR);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
#endif
}
#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
int checkboard(void)
{
sys_info_t sysinfo;
unsigned char *s = getenv("serial#");
get_sys_info(&sysinfo);
printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
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