pip405.c

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/*
 * (C) Copyright 2001
 * Denis Peter, MPL AG Switzerland, [e-mail]
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 *
 * TODO: clean-up
 */

#include <common.h>
#include "pip405.h"
#include <asm/processor.h>
#include <i2c.h>
#include "../common/isa.h"
#include "../common/common_util.h"

#undef SDRAM_DEBUG

#define FALSE           0
#define TRUE            1

/* stdlib.h causes some compatibility problems; should fixe these! -- wd */
#ifndef __ldiv_t_defined
typedef struct {
	long int quot;		/* Quotient */
	long int rem;		/* Remainder    */
} ldiv_t;
extern ldiv_t ldiv (long int __numer, long int __denom);

# define __ldiv_t_defined	1
#endif


typedef enum {
	SDRAM_NO_ERR,
	SDRAM_SPD_COMM_ERR,
	SDRAM_SPD_CHKSUM_ERR,
	SDRAM_UNSUPPORTED_ERR,
	SDRAM_UNKNOWN_ERR
} SDRAM_ERR;

typedef struct {
	const unsigned char mode;
	const unsigned char row;
	const unsigned char col;
	const unsigned char bank;
} SDRAM_SETUP;

static const SDRAM_SETUP sdram_setup_table[] = {
	{1, 11, 9, 2},
	{1, 11, 10, 2},
	{2, 12, 9, 4},
	{2, 12, 10, 4},
	{3, 13, 9, 4},
	{3, 13, 10, 4},
	{3, 13, 11, 4},
	{4, 12, 8, 2},
	{4, 12, 8, 4},
	{5, 11, 8, 2},
	{5, 11, 8, 4},
	{6, 13, 8, 2},
	{6, 13, 8, 4},
	{7, 13, 9, 2},
	{7, 13, 10, 2},
	{0, 0, 0, 0}
};

static const unsigned char cal_indextable[] = {
	9, 23, 25
};


/*
 * translate ns.ns/10 coding of SPD timing values
 * into 10 ps unit values
 */

unsigned short NS10to10PS (unsigned char spd_byte, unsigned char spd_version)
{
	unsigned short ns, ns10;

	/* isolate upper nibble */
	ns = (spd_byte >> 4) & 0x0F;
	/* isolate lower nibble */
	ns10 = (spd_byte & 0x0F);

	return (ns * 100 + ns10 * 10);
}

/*
 * translate ns.ns/4 coding of SPD timing values
 * into 10 ps unit values
 */

unsigned short NS4to10PS (unsigned char spd_byte, unsigned char spd_version)
{
	unsigned short ns, ns4;

	/* isolate upper 6 bits */
	ns = (spd_byte >> 2) & 0x3F;
	/* isloate lower 2 bits */
	ns4 = (spd_byte & 0x03);

	return (ns * 100 + ns4 * 25);
}

/*
 * translate ns coding of SPD timing values
 * into 10 ps unit values
 */

unsigned short NSto10PS (unsigned char spd_byte)
{
	return (spd_byte * 100);
}

void SDRAM_err (const char *s)
{
#ifndef SDRAM_DEBUG
	DECLARE_GLOBAL_DATA_PTR;

	(void) get_clocks ();
	gd->baudrate = 9600;
	serial_init ();
#endif
	serial_puts ("\n");
	serial_puts (s);
	serial_puts ("\n enable SDRAM_DEBUG for more info\n");
	for (;;);
}


#ifdef SDRAM_DEBUG

void write_hex (unsigned char i)
{
	char cc;

	cc = i >> 4;
	cc &= 0xf;
	if (cc > 9)
		serial_putc (cc + 55);
	else
		serial_putc (cc + 48);
	cc = i & 0xf;
	if (cc > 9)
		serial_putc (cc + 55);
	else
		serial_putc (cc + 48);
}

void write_4hex (unsigned long val)
{
	write_hex ((unsigned char) (val >> 24));
	write_hex ((unsigned char) (val >> 16));
	write_hex ((unsigned char) (val >> 8));
	write_hex ((unsigned char) val);
}

#endif

int board_early_init_f (void)
{
	unsigned char dataout[1];
	unsigned char datain[128];
	unsigned long sdram_size;
	SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table;
	unsigned long memclk;
	unsigned long tmemclk = 0;
	unsigned long tmp, bank, baseaddr, bank_size;
	unsigned short i;
	unsigned char rows, cols, banks, sdram_banks, density;
	unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks,
			trc_clocks, tctp_clocks;
	unsigned char cal_index, cal_val, spd_version, spd_chksum;
	unsigned char buf[8];
#ifdef SDRAM_DEBUG
	DECLARE_GLOBAL_DATA_PTR;
#endif
	/* set up the config port */
	mtdcr (ebccfga, pb7ap);
	mtdcr (ebccfgd, CONFIG_PORT_AP);
	mtdcr (ebccfga, pb7cr);
	mtdcr (ebccfgd, CONFIG_PORT_CR);

	memclk = get_bus_freq (tmemclk);
	tmemclk = 1000000000 / (memclk / 100);	/* in 10 ps units */

#ifdef SDRAM_DEBUG
	(void) get_clocks ();
	gd->baudrate = 9600;
	serial_init ();
	serial_puts ("\nstart SDRAM Setup\n");
#endif

	/* Read Serial Presence Detect Information */
	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
	dataout[0] = 0;
	for (i = 0; i < 128; i++)
		datain[i] = 127;
	i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128);
#ifdef SDRAM_DEBUG
	serial_puts ("\ni2c_read returns ");
	write_hex (i);
	serial_puts ("\n");
#endif

#ifdef SDRAM_DEBUG
	for (i = 0; i < 128; i++) {
		write_hex (datain[i]);
		serial_puts (" ");
		if (((i + 1) % 16) == 0)
			serial_puts ("\n");
	}
	serial_puts ("\n");
#endif
	spd_chksum = 0;
	for (i = 0; i < 63; i++) {
		spd_chksum += datain[i];
	}							/* endfor */
	if (datain[63] != spd_chksum) {
#ifdef SDRAM_DEBUG
		serial_puts ("SPD chksum: 0x");
		write_hex (datain[63]);
		serial_puts (" != calc. chksum: 0x");
		write_hex (spd_chksum);
		serial_puts ("\n");
#endif
		SDRAM_err ("SPD checksum Error");
	}
	/* SPD seems to be ok, use it */

	/* get SPD version */
	spd_version = datain[62];

	/* do some sanity checks on the kind of RAM */
	if ((datain[0] < 0x80) ||	/* less than 128 valid bytes in SPD */
		(datain[2] != 0x04) ||	/* if not SDRAM */
		(!((datain[6] == 0x40) || (datain[6] == 0x48))) ||	/* or not (64 Bit or 72 Bit)  */
		(datain[7] != 0x00) || (datain[8] != 0x01) ||	/* or not LVTTL signal levels */
		(datain[126] == 0x66))	/* or a 66Mhz modules */
		SDRAM_err ("unsupported SDRAM");
#ifdef SDRAM_DEBUG
	serial_puts ("SDRAM sanity ok\n");
#endif

	/* get number of rows/cols/banks out of byte 3+4+5 */
	rows = datain[3];
	cols = datain[4];
	banks = datain[5];

	/* get number of SDRAM banks out of byte 17 and
	   supported CAS latencies out of byte 18 */
	sdram_banks = datain[17];
	supported_cal = datain[18] & ~0x81;

	while (t->mode != 0) {
		if ((t->row == rows) && (t->col == cols)
			&& (t->bank == sdram_banks))
			break;
		t++;
	}							/* endwhile */

#ifdef SDRAM_DEBUG
	serial_puts ("rows: ");
	write_hex (rows);
	serial_puts (" cols: ");
	write_hex (cols);
	serial_puts (" banks: ");
	write_hex (banks);
	serial_puts (" mode: ");
	write_hex (t->mode);
	serial_puts ("\n");
#endif
	if (t->mode == 0)
		SDRAM_err ("unsupported SDRAM");
	/* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */
#ifdef SDRAM_DEBUG
	serial_puts ("tRP: ");
	write_hex (datain[27]);
	serial_puts ("\ntRCD: ");
	write_hex (datain[29]);
	serial_puts ("\ntRAS: ");
	write_hex (datain[30]);
	serial_puts ("\n");
#endif

	trp_clocks = (NSto10PS (datain[27]) + (tmemclk - 1)) / tmemclk;
	trcd_clocks = (NSto10PS (datain[29]) + (tmemclk - 1)) / tmemclk;
	tras_clocks = (NSto10PS (datain[30]) + (tmemclk - 1)) / tmemclk;
	density = datain[31];

	/* trc_clocks is sum of trp_clocks + tras_clocks */
	trc_clocks = trp_clocks + tras_clocks;
	/* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
	tctp_clocks =
			((NSto10PS (datain[30]) - NSto10PS (datain[29])) +
			 (tmemclk - 1)) / tmemclk;

#ifdef SDRAM_DEBUG
	serial_puts ("c_RP: ");
	write_hex (trp_clocks);
	serial_puts ("\nc_RCD: ");
	write_hex (trcd_clocks);
	serial_puts ("\nc_RAS: ");
	write_hex (tras_clocks);
	serial_puts ("\nc_RC: (RP+RAS): ");
	write_hex (trc_clocks);
	serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): ");
	write_hex (tctp_clocks);
	serial_puts ("\nt_CTP: RAS - RCD: ");
	write_hex ((unsigned
				char) ((NSto10PS (datain[30]) -
						NSto10PS (datain[29])) >> 8));
	write_hex ((unsigned char) (NSto10PS (datain[30]) - NSto10PS (datain[29])));
	serial_puts ("\ntmemclk: ");
	write_hex ((unsigned char) (tmemclk >> 8));
	write_hex ((unsigned char) (tmemclk));
	serial_puts ("\n");
#endif


	cal_val = 255;
	for (i = 6, cal_index = 0; (i > 0) && (cal_index < 3); i--) {
		/* is this CAS latency supported ? */
		if ((supported_cal >> i) & 0x01) {
			buf[0] = datain[cal_indextable[cal_index]];
			if (cal_index < 2) {
				if (NS10to10PS (buf[0], spd_version) <= tmemclk)
					cal_val = i;
			} else {
				/* SPD bytes 25+26 have another format */
				if (NS4to10PS (buf[0], spd_version) <= tmemclk)
					cal_val = i;
			}	/* endif */
			cal_index++;
		}	/* endif */
	}	/* endfor */
#ifdef SDRAM_DEBUG
	serial_puts ("CAL: ");
	write_hex (cal_val + 1);
	serial_puts ("\n");
#endif

	if (cal_val == 255)
		SDRAM_err ("unsupported SDRAM");

	/* get SDRAM timing register */
	mtdcr (memcfga, mem_sdtr1);
	tmp = mfdcr (memcfgd) & ~0x018FC01F;
	/* insert CASL value */
/*  tmp |= ((unsigned long)cal_val) << 23; */
	tmp |= ((unsigned long) cal_val) << 23;
	/* insert PTA value */
	tmp |= ((unsigned long) (trp_clocks - 1)) << 18;
	/* insert CTP value */
/*  tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */
	tmp |= ((unsigned long) (trc_clocks - trp_clocks - trcd_clocks)) << 16;
	/* insert LDF (always 01) */
	tmp |= ((unsigned long) 0x01) << 14;
	/* insert RFTA value */
	tmp |= ((unsigned long) (trc_clocks - 4)) << 2;
	/* insert RCD value */
	tmp |= ((unsigned long) (trcd_clocks - 1)) << 0;

#ifdef SDRAM_DEBUG
	serial_puts ("sdtr: ");
	write_4hex (tmp);
	serial_puts ("\n");
#endif

	/* write SDRAM timing register */
	mtdcr (memcfga, mem_sdtr1);
	mtdcr (memcfgd, tmp);
	baseaddr = CFG_SDRAM_BASE;
	bank_size = (((unsigned long) density) << 22) / 2;
	/* insert AM value */
	tmp = ((unsigned long) t->mode - 1) << 13;
	/* insert SZ value; */
	switch (bank_size) {
	case 0x00400000:
		tmp |= ((unsigned long) 0x00) << 17;
		break;
	case 0x00800000:
		tmp |= ((unsigned long) 0x01) << 17;
		break;
	case 0x01000000:
		tmp |= ((unsigned long) 0x02) << 17;
		break;
	case 0x02000000:
		tmp |= ((unsigned long) 0x03) << 17;
		break;
	case 0x04000000:
		tmp |= ((unsigned long) 0x04) << 17;
		break;
	case 0x08000000:
		tmp |= ((unsigned long) 0x05) << 17;
		break;
	case 0x10000000:
		tmp |= ((unsigned long) 0x06) << 17;
		break;
	default:
		SDRAM_err ("unsupported SDRAM");
	}	/* endswitch */
	/* get SDRAM bank 0 register */
	mtdcr (memcfga, mem_mb0cf);
	bank = mfdcr (memcfgd) & ~0xFFCEE001;
	bank |= (baseaddr | tmp | 0x01);
#ifdef SDRAM_DEBUG
	serial_puts ("bank0: baseaddr: ");
	write_4hex (baseaddr);
	serial_puts (" banksize: ");
	write_4hex (bank_size);
	serial_puts (" mb0cf: ");
	write_4hex (bank);
	serial_puts ("\n");
#endif
	baseaddr += bank_size;
	sdram_size += bank_size;

	/* write SDRAM bank 0 register */
	mtdcr (memcfga, mem_mb0cf);
	mtdcr (memcfgd, bank);

	/* get SDRAM bank 1 register */
	mtdcr (memcfga, mem_mb1cf);
	bank = mfdcr (memcfgd) & ~0xFFCEE001;
	sdram_size = 0;

#ifdef SDRAM_DEBUG
	serial_puts ("bank1: baseaddr: ");
	write_4hex (baseaddr);
	serial_puts (" banksize: ");
	write_4hex (bank_size);
#endif
	if (banks == 2) {
		bank |= (baseaddr | tmp | 0x01);
		baseaddr += bank_size;
		sdram_size += bank_size;
	}	/* endif */
#ifdef SDRAM_DEBUG
	serial_puts (" mb1cf: ");
	write_4hex (bank);
	serial_puts ("\n");
#endif
	/* write SDRAM bank 1 register */
	mtdcr (memcfga, mem_mb1cf);
	mtdcr (memcfgd, bank);

	/* get SDRAM bank 2 register */
	mtdcr (memcfga, mem_mb2cf);
	bank = mfdcr (memcfgd) & ~0xFFCEE001;

	bank |= (baseaddr | tmp | 0x01);

#ifdef SDRAM_DEBUG
	serial_puts ("bank2: baseaddr: ");
	write_4hex (baseaddr);
	serial_puts (" banksize: ");
	write_4hex (bank_size);
	serial_puts (" mb2cf: ");
	write_4hex (bank);
	serial_puts ("\n");
#endif