mip405.c

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	mtdcr (memcfgd, tmp);
	/* enable ECC if used */
#if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI)
	if (sdram_table[i].ecc) {
		/* disable checking for all banks */
		unsigned long	*p;
#ifdef SDRAM_DEBUG
		serial_puts ("disable ECC.. ");
#endif
		mtdcr (memcfga, mem_ecccf);
		tmp = mfdcr (memcfgd);
		tmp &= 0xff0fffff;		/* disable all banks */
		mtdcr (memcfga, mem_ecccf);
		/* set up SDRAM Controller with ECC enabled */
#ifdef SDRAM_DEBUG
		serial_puts ("setup SDRAM Controller.. ");
#endif
		mtdcr (memcfgd, tmp);
		mtdcr (memcfga, mem_mcopt1);
		tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000;
		mtdcr (memcfga, mem_mcopt1);
		mtdcr (memcfgd, tmp);
		udelay (600);
#ifdef SDRAM_DEBUG
		serial_puts ("fill the memory..\n");
#endif
		serial_puts (".");
		/* now, fill all the memory */
		tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz);
		p = (unsigned long) 0;
		while ((unsigned long) p < tmp) {
			*p++ = 0L;
			if (!((unsigned long) p % 0x00800000))	/* every 8MByte */
				serial_puts (".");
		}
		/* enable bank 0 */
		serial_puts (".");
#ifdef SDRAM_DEBUG
		serial_puts ("enable ECC\n");
#endif
		udelay (400);
		mtdcr (memcfga, mem_ecccf);
		tmp = mfdcr (memcfgd);
		tmp |= 0x00800000;		/* enable bank 0 */
		mtdcr (memcfgd, tmp);
		udelay (400);
	} else
#endif
	{
		/* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
		mtdcr (memcfga, mem_mcopt1);
		tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80C00000;
		mtdcr (memcfga, mem_mcopt1);
		mtdcr (memcfgd, tmp);
		udelay (400);
	}
	serial_puts ("\n");
	return (0);
}

int board_early_init_f (void)
{
	init_sdram ();

   /*-------------------------------------------------------------------------+
   | Interrupt controller setup for the PIP405 board.
   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
   |       IRQ 16    405GP internally generated; active low; level sensitive
   |       IRQ 17-24 RESERVED
   |       IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive
   |       IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
   |       IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
   | Note for MIP405 board:
   |       An interrupt taken for the SouthBridge (IRQ 25) indicates that
   |       the Interrupt Controller in the South Bridge has caused the
   |       interrupt. The IC must be read to determine which device
   |       caused the interrupt.
   |
   +-------------------------------------------------------------------------*/
	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
	mtdcr (uicer, 0x00000000);	/* disable all ints */
	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical (for now) */
	mtdcr (uicpr, 0xFFFFFF80);	/* set int polarities */
	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
	return 0;
}


/*
 * Get some PLD Registers
 */

unsigned short get_pld_parvers (void)
{
	unsigned short result;
	unsigned char rc;

	rc = in8 (PLD_PART_REG);
	result = (unsigned short) rc << 8;
	rc = in8 (PLD_VERS_REG);
	result |= rc;
	return result;
}


void user_led0 (unsigned char on)
{
	if (on)
		out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4));
	else
		out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb));
}


void ide_set_reset (int idereset)
{
	/* if reset = 1 IDE reset will be asserted */
	if (idereset)
		out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1));
	else {
		udelay (10000);
		out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe));
	}
}


/* ------------------------------------------------------------------------- */

void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var)
{
#if !defined(CONFIG_MIP405T)
	unsigned char bc,rc,tmp;
	int i;

	bc = in8 (PLD_BOARD_CFG_REG);
	tmp = ~bc;
	tmp &= 0xf;
	rc = 0;
	for (i = 0; i < 4; i++) {
		rc <<= 1;
		rc += (tmp & 0x1);
		tmp >>= 1;
	}
	rc++;
	if((  (((bc>>4) & 0xf)==0x2) /* Rev C PCB or */
	   || (((bc>>4) & 0xf)==0x1)) /* Rev B PCB with */
		&& (rc==0x1))     /* Population Option 1 is a -3 */
		rc=3;
	*pcbrev=(bc >> 4) & 0xf;
	*var=rc;
#else
	unsigned char bc;
	bc = in8 (PLD_BOARD_CFG_REG);
	*pcbrev=(bc >> 4) & 0xf;
	*var=16-(bc & 0xf);
#endif
}

/*
 * Check Board Identity:
 */
/* serial String: "MIP405_1000" OR "MIP405T_1000" */
#if !defined(CONFIG_MIP405T)
#define BOARD_NAME	"MIP405"
#else
#define BOARD_NAME	"MIP405T"
#endif

int checkboard (void)
{
	unsigned char s[50];
	unsigned char bc, var;
	int i;
	backup_t *b = (backup_t *) s;

	puts ("Board: ");
	get_pcbrev_var(&bc,&var);
	i = getenv_r ("serial#", s, 32);
	if ((i == 0) || strncmp (s, BOARD_NAME,sizeof(BOARD_NAME))) {
		get_backup_values (b);
		if (strncmp (b->signature, "MPL\0", 4) != 0) {
			puts ("### No HW ID - assuming " BOARD_NAME);
			printf ("-%d Rev %c", var, 'A' + bc);
		} else {
			b->serial_name[sizeof(BOARD_NAME)-1] = 0;
			printf ("%s-%d Rev %c SN: %s", b->serial_name, var,
					'A' + bc, &b->serial_name[sizeof(BOARD_NAME)]);
		}
	} else {
		s[sizeof(BOARD_NAME)-1] = 0;
		printf ("%s-%d Rev %c SN: %s", s, var,'A' + bc,
				&s[sizeof(BOARD_NAME)]);
	}
	bc = in8 (PLD_EXT_CONF_REG);
	printf (" Boot Config: 0x%x\n", bc);
	return (0);
}


/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
/*
  initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
  the necessary info for SDRAM controller configuration
*/
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
static int test_dram (unsigned long ramsize);

long int initdram (int board_type)
{

	unsigned long bank_reg[4], tmp, bank_size;
	int i, ds;
	unsigned long TotalSize;

	ds = 0;
	/* since the DRAM controller is allready set up, calculate the size with the
	   bank registers    */
	mtdcr (memcfga, mem_mb0cf);
	bank_reg[0] = mfdcr (memcfgd);
	mtdcr (memcfga, mem_mb1cf);
	bank_reg[1] = mfdcr (memcfgd);
	mtdcr (memcfga, mem_mb2cf);
	bank_reg[2] = mfdcr (memcfgd);
	mtdcr (memcfga, mem_mb3cf);
	bank_reg[3] = mfdcr (memcfgd);
	TotalSize = 0;
	for (i = 0; i < 4; i++) {
		if ((bank_reg[i] & 0x1) == 0x1) {
			tmp = (bank_reg[i] >> 17) & 0x7;
			bank_size = 4 << tmp;
			TotalSize += bank_size;
		} else
			ds = 1;
	}
	mtdcr (memcfga, mem_ecccf);
	tmp = mfdcr (memcfgd);

	if (!tmp)
		printf ("No ");
	printf ("ECC ");

	test_dram (TotalSize * MEGA_BYTE);
	return (TotalSize * MEGA_BYTE);
}

/* ------------------------------------------------------------------------- */


static int test_dram (unsigned long ramsize)
{
#ifdef SDRAM_DEBUG
	mem_test (0L, ramsize, 1);
#endif
	/* not yet implemented */
	return (1);
}

/* used to check if the time in RTC is valid */
static unsigned long start;
static struct rtc_time tm;
extern flash_info_t flash_info[];	/* info for FLASH chips */

int misc_init_r (void)
{
	DECLARE_GLOBAL_DATA_PTR;
	/* adjust flash start and size as well as the offset */
	gd->bd->bi_flashstart=0-flash_info[0].size;
	gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN;
	gd->bd->bi_flashoffset=0;

	/* check, if RTC is running */
	rtc_get (&tm);
	start=get_timer(0);
	/* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
	if (mfdcr(strap) & PSR_ROM_LOC)
	       mtspr(ccr0, (mfspr(ccr0) & ~0x80));

	return (0);
}


void print_mip405_rev (void)
{
	unsigned char part, vers, pcbrev, var;

	get_pcbrev_var(&pcbrev,&var);
	part = in8 (PLD_PART_REG);
	vers = in8 (PLD_VERS_REG);
	printf ("Rev:   " BOARD_NAME "-%d Rev %c PLD %d Vers %d\n",
			var, pcbrev + 'A', part & 0x7F, vers);
}


#ifdef CONFIG_POST
/*
 * Returns 1 if keys pressed to start the power-on long-running tests
 * Called from board_init_f().
 */
int post_hotkeys_pressed(void)
{
	return 0;	/* No hotkeys supported */
}
#endif

extern void mem_test_reloc(void);
extern int mk_date (char *, struct rtc_time *);

int last_stage_init (void)
{
	unsigned long stop;
	struct rtc_time newtm;
	unsigned char *s;
	mem_test_reloc();
	/* write correct LED configuration */
	if (miiphy_write (0x1, 0x14, 0x2402) != 0) {
		printf ("Error writing to the PHY\n");
	}
	/* since LED/CFG2 is not connected on the -2,
	 * write to correct capability information */
	if (miiphy_write (0x1, 0x4, 0x01E1) != 0) {
		printf ("Error writing to the PHY\n");
	}
	print_mip405_rev ();
	show_stdio_dev ();
	check_env ();
	/* check if RTC time is valid */
	stop=get_timer(start);
	while(stop<1200) {   /* we wait 1.2 sec to check if the RTC is running */
		udelay(1000);
		stop=get_timer(start);
	}
	rtc_get (&newtm);
	if(tm.tm_sec==newtm.tm_sec) {
		s=getenv("defaultdate");
		if(!s)
			mk_date ("010112001970", &newtm);
		else
			if(mk_date (s, &newtm)!=0) {
				printf("RTC: Bad date format in defaultdate\n");
				return 0;
			}
		rtc_reset ();
		rtc_set(&newtm);
	}
	return 0;
}

/***************************************************************************
 * some helping routines
 */

int overwrite_console (void)
{
	return ((in8 (PLD_EXT_CONF_REG) & 0x1)==0);	/* return TRUE if console should be overwritten */
}


/************************************************************************
* Print MIP405 Info
************************************************************************/
void print_mip405_info (void)
{
	unsigned char part, vers, cfg, irq_reg, com_mode, ext;

	part = in8 (PLD_PART_REG);
	vers = in8 (PLD_VERS_REG);
	cfg = in8 (PLD_BOARD_CFG_REG);
	irq_reg = in8 (PLD_IRQ_REG);
	com_mode = in8 (PLD_COM_MODE_REG);
	ext = in8 (PLD_EXT_CONF_REG);

	printf ("PLD Part %d version %d\n", part & 0x7F, vers);
	printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A');
	printf ("Population Options %d %d %d %d\n", (cfg) & 0x1,
			(cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1);
	printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off");
	printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3);
#if !defined(CONFIG_MIP405T)
	printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
			(ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
			(ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
			(ext >> 6) & 0x1, (ext >> 7) & 0x1);
	printf ("SER1 uses handshakes %s\n",
			(ext & 0x80) ? "DTR/DSR" : "RTS/CTS");
#else
	printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
			(ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
			(ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
			(ext >> 6) & 0x1,(ext >> 7) & 0x1);
#endif
	printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted");
	printf ("IRQs:\n");
	printf ("  PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active");
#if !defined(CONFIG_MIP405T)
	printf ("  UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active");
	printf ("  UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active");
#endif
	printf ("  PIIX SMI:  %s\n", (irq_reg & 0x10) ? "inactive" : "active");
	printf ("  PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active");
	printf ("  PIIX NMI:  %s\n", (irq_reg & 0x4) ? "inactive" : "active");
}