mv_gen_reg.h
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/****************************************/
#define PCI_CS_0_BASE_ADDRESS 0x110
#define PCI_CS_1_BASE_ADDRESS 0x114
#define PCI_CS_2_BASE_ADDRESS 0x118
#define PCI_CS_3_BASE_ADDRESS 0x11c
#define PCI_BOOTCS_BASE_ADDRESS 0x120
/****************************************/
/* PCI Configuration Function 2 */
/****************************************/
#define PCI_P2P_MEM0_BASE_ADDRESS 0x210
/*#define PCI_P2P_MEM1_BASE_ADDRESS 0x2141 */
#define PCI_P2P_I_O_BASE_ADDRESS 0x218
/*#define PCI_CPU_BASE_ADDRESS 0x21c1 */
/****************************************/
/* PCI Configuration Function 4 */
/****************************************/
#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410
#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414
#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418
#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c
#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420
#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424
/****************************************/
/* PCI Configuration Function 5 */
/****************************************/
#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510
#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514
#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518
#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c
#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520
#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524
/****************************************/
/* PCI Configuration Function 6 */
/****************************************/
#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610
#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614
#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618
#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c
#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620
#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624
/****************************************/
/* PCI Configuration Function 7 */
/****************************************/
#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710
#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714
#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718
#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c
#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720
#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724
/****************************** MV64360 and MV64460 PCI ***************************/
/***********************************/
/* PCI Control Register Map */
/***********************************/
#define PCI_0_DLL_STATUS_AND_COMMAND 0x1d20
#define PCI_1_DLL_STATUS_AND_COMMAND 0x1da0
#define PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C
#define PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C
#define PCI_0_COMMAND 0xc00
#define PCI_1_COMMAND 0xc80
#define PCI_0_MODE 0xd00
#define PCI_1_MODE 0xd80
#define PCI_0_RETRY 0xc04
#define PCI_1_RETRY 0xc84
#define PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04
#define PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84
#define PCI_0_MSI_TRIGGER_TIMER 0xc38
#define PCI_1_MSI_TRIGGER_TIMER 0xcb8
#define PCI_0_ARBITER_CONTROL 0x1d00
#define PCI_1_ARBITER_CONTROL 0x1d80
#define PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08
#define PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88
#define PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c
#define PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c
#define PCI_0_CROSS_BAR_TIMEOUT 0x1d04
#define PCI_1_CROSS_BAR_TIMEOUT 0x1d84
#define PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18
#define PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98
#define PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10
#define PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90
#define PCI_0_P2P_CONFIG 0x1d14
#define PCI_1_P2P_CONFIG 0x1d94
#define PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00
#define PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04
#define PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08
#define PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10
#define PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14
#define PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18
#define PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20
#define PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24
#define PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28
#define PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30
#define PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34
#define PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38
#define PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40
#define PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44
#define PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48
#define PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50
#define PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54
#define PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58
#define PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80
#define PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84
#define PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88
#define PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90
#define PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94
#define PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98
#define PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0
#define PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
#define PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8
#define PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0
#define PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
#define PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8
#define PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0
#define PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
#define PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8
#define PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0
#define PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
#define PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8
/****************************************/
/* PCI Configuration Access Registers */
/****************************************/
#define PCI_0_CONFIG_ADDR 0xcf8
#define PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc
#define PCI_1_CONFIG_ADDR 0xc78
#define PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c
#define PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34
#define PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4
/****************************************/
/* PCI Error Report Registers */
/****************************************/
#define PCI_0_SERR_MASK 0xc28
#define PCI_1_SERR_MASK 0xca8
#define PCI_0_ERROR_ADDR_LOW 0x1d40
#define PCI_1_ERROR_ADDR_LOW 0x1dc0
#define PCI_0_ERROR_ADDR_HIGH 0x1d44
#define PCI_1_ERROR_ADDR_HIGH 0x1dc4
#define PCI_0_ERROR_ATTRIBUTE 0x1d48
#define PCI_1_ERROR_ATTRIBUTE 0x1dc8
#define PCI_0_ERROR_COMMAND 0x1d50
#define PCI_1_ERROR_COMMAND 0x1dd0
#define PCI_0_ERROR_CAUSE 0x1d58
#define PCI_1_ERROR_CAUSE 0x1dd8
#define PCI_0_ERROR_MASK 0x1d5c
#define PCI_1_ERROR_MASK 0x1ddc
/****************************************/
/* PCI Debug Registers */
/****************************************/
#define PCI_0_MMASK 0X1D24
#define PCI_1_MMASK 0X1DA4
/*********************************************/
/* PCI Configuration, Function 0, Registers */
/*********************************************/
#define PCI_DEVICE_AND_VENDOR_ID 0x000
#define PCI_STATUS_AND_COMMAND 0x004
#define PCI_CLASS_CODE_AND_REVISION_ID 0x008
#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
#define PCI_SCS_0_BASE_ADDR_LOW 0x010
#define PCI_SCS_0_BASE_ADDR_HIGH 0x014
#define PCI_SCS_1_BASE_ADDR_LOW 0x018
#define PCI_SCS_1_BASE_ADDR_HIGH 0x01C
#define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020
#define PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024
/*#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c1 */
#define PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030
#define PCI_CAPABILTY_LIST_POINTER 0x034
#define PCI_INTERRUPT_PIN_AND_LINE 0x03C
/* capability list */
#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040
#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
#define PCI_VPD_ADDR 0x048
#define PCI_VPD_DATA 0x04c
#define PCI_MSI_MESSAGE_CONTROL 0x050
#define PCI_MSI_MESSAGE_ADDR 0x054
#define PCI_MSI_MESSAGE_UPPER_ADDR 0x058
#define PCI_MSI_MESSAGE_DATA 0x05c
#define PCI_X_COMMAND 0x060
#define PCI_X_STATUS 0x064
#define PCI_COMPACT_PCI_HOT_SWAP 0x068
/***********************************************/
/* PCI Configuration, Function 1, Registers */
/***********************************************/
#define PCI_SCS_2_BASE_ADDR_LOW 0x110
#define PCI_SCS_2_BASE_ADDR_HIGH 0x114
#define PCI_SCS_3_BASE_ADDR_LOW 0x118
#define PCI_SCS_3_BASE_ADDR_HIGH 0x11c
#define PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120
#define PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124
/***********************************************/
/* PCI Configuration, Function 2, Registers */
/***********************************************/
#define PCI_DEVCS_0_BASE_ADDR_LOW 0x210
#define PCI_DEVCS_0_BASE_ADDR_HIGH 0x214
#define PCI_DEVCS_1_BASE_ADDR_LOW 0x218
#define PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c
#define PCI_DEVCS_2_BASE_ADDR_LOW 0x220
#define PCI_DEVCS_2_BASE_ADDR_HIGH 0x224
/***********************************************/
/* PCI Configuration, Function 3, Registers */
/***********************************************/
#define PCI_DEVCS_3_BASE_ADDR_LOW 0x310
#define PCI_DEVCS_3_BASE_ADDR_HIGH 0x314
#define PCI_BOOT_CS_BASE_ADDR_LOW 0x318
#define PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c
#define PCI_CPU_BASE_ADDR_LOW 0x220
#define PCI_CPU_BASE_ADDR_HIGH 0x224
/***********************************************/
/* PCI Configuration, Function 4, Registers */
/***********************************************/
#define PCI_P2P_MEM0_BASE_ADDR_LOW 0x410
#define PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414
#define PCI_P2P_MEM1_BASE_ADDR_LOW 0x418
#define PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c
#define PCI_P2P_I_O_BASE_ADDR 0x420
#define PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424
/****************************** MV64360 and MV64460 PCI End ***************************/
/****************************************/
/* I20 Support registers */
/****************************************/
#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010
#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014
#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018
#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01C
#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020
#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024
#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028
#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02C
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030
#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044
#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050
#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054
#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060
#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064
#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068
#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06C
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07C
#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C10
#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C14
#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C18
#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C1C
#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C20
#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C24
#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C28
#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C2C
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C30
#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C34
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C40
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C44
#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1C50
#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1C54
#define INBOUND_FREE_H⌨️ 快捷键说明
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