mv_gen_reg.h

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/* mv_gen_reg.h - Internal registers definition file */
/* Copyright - Galileo technology. */


/*******************************************************************************
*		    Copyright 2002, GALILEO TECHNOLOGY, LTD.		       *
* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL.		       *
* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT  *
* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE	       *
* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.     *
* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED,       *
* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.   *
*									       *
* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, *
* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL    *
* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K.  *
* (MJKK), GALILEO TECHNOLOGY LTD. (GTL) AND GALILEO TECHNOLOGY, INC. (GTI).    *
********************************************************************************
* mv_gen_reg.h - Marvell 64360 and 64460 Internal registers definition file.
*
* DESCRIPTION:
*	None.
*
* DEPENDENCIES:
*	None.
*
*******************************************************************************/

#ifndef __INCmv_gen_regh
#define __INCmv_gen_regh


/* Supported by the Atlantis */
#define INCLUDE_PCI_1
#define INCLUDE_PCI_0_ARBITER
#define INCLUDE_PCI_1_ARBITER
#define INCLUDE_SNOOP_SUPPORT
#define INCLUDE_P2P
#define INCLUDE_ETH_PORT_2
#define INCLUDE_CPU_MAPPING
#define INCLUDE_MPSC

/* Not supported features */
#undef	INCLUDE_CNTMR_4_7
#undef	INCLUDE_DMA_4_7


/****************************************/
/* Processor Address Space				*/
/****************************************/
/* DDR SDRAM BAR and size registers */

/* Sdram's BAR'S */
#define SCS_0_LOW_DECODE_ADDRESS			0x008
#define SCS_0_HIGH_DECODE_ADDRESS			0x010
#define SCS_1_LOW_DECODE_ADDRESS			0x208
#define SCS_1_HIGH_DECODE_ADDRESS			0x210
#define SCS_2_LOW_DECODE_ADDRESS			0x018
#define SCS_2_HIGH_DECODE_ADDRESS			0x020
#define SCS_3_LOW_DECODE_ADDRESS			0x218
#define SCS_3_HIGH_DECODE_ADDRESS			0x220

/* Make it fit the MV64360 and MV64460 Lowlevel driver */
#define CS_0_BASE_ADDR			SCS_0_LOW_DECODE_ADDRESS
#define CS_0_SIZE			SCS_0_HIGH_DECODE_ADDRESS
#define CS_1_BASE_ADDR		SCS_1_LOW_DECODE_ADDRESS
#define CS_1_SIZE			SCS_1_HIGH_DECODE_ADDRESS
#define CS_2_BASE_ADDR		SCS_2_LOW_DECODE_ADDRESS
#define CS_2_SIZE			SCS_2_HIGH_DECODE_ADDRESS
#define CS_3_BASE_ADDR		SCS_3_LOW_DECODE_ADDRESS
#define CS_3_SIZE			SCS_3_HIGH_DECODE_ADDRESS

/* Devices BAR'S */
#define CS_0_LOW_DECODE_ADDRESS			0x028
#define CS_0_HIGH_DECODE_ADDRESS			0x030
#define CS_1_LOW_DECODE_ADDRESS			0x228
#define CS_1_HIGH_DECODE_ADDRESS			0x230
#define CS_2_LOW_DECODE_ADDRESS			0x248
#define CS_2_HIGH_DECODE_ADDRESS			0x250
#define CS_3_LOW_DECODE_ADDRESS			0x038
#define CS_3_HIGH_DECODE_ADDRESS			0x040
#define BOOTCS_LOW_DECODE_ADDRESS			0x238
#define BOOTCS_HIGH_DECODE_ADDRESS			0x240

/* Make it fit the MV64360 and MV64460 Lowlevel driver */
/* Devices BAR and size registers */

#define DEV_CS0_BASE_ADDR	CS_0_LOW_DECODE_ADDRESS
#define DEV_CS0_SIZE			CS_0_HIGH_DECODE_ADDRESS
#define DEV_CS1_BASE_ADDR	CS_1_LOW_DECODE_ADDRESS
#define DEV_CS1_SIZE		CS_1_HIGH_DECODE_ADDRESS
#define DEV_CS2_BASE_ADDR	CS_2_LOW_DECODE_ADDRESS
#define DEV_CS2_SIZE			CS_2_HIGH_DECODE_ADDRESS
#define DEV_CS3_BASE_ADDR		CS_3_LOW_DECODE_ADDRESS
#define DEV_CS3_SIZE		CS_3_HIGH_DECODE_ADDRESS
#define BOOTCS_BASE_ADDR	BOOTCS_LOW_DECODE_ADDRESS
#define BOOTCS_SIZE		BOOTCS_HIGH_DECODE_ADDRESS

/* PCI 0 BAR and size registers	 old names of evb64260*/

#define PCI_0I_O_LOW_DECODE_ADDRESS			0x048
#define PCI_0I_O_HIGH_DECODE_ADDRESS			0x050
#define PCI_0MEMORY0_LOW_DECODE_ADDRESS		0x058
#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS		0x060
#define PCI_0MEMORY1_LOW_DECODE_ADDRESS		0x080
#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS		0x088
#define PCI_0MEMORY2_LOW_DECODE_ADDRESS		0x258
#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS		0x260
#define PCI_0MEMORY3_LOW_DECODE_ADDRESS		0x280
#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS		0x288

/* Make it fit the MV64360 and MV64460 Lowlevel driver */
#define PCI_0_IO_BASE_ADDR						0x048
#define PCI_0_IO_SIZE							0x050
#define PCI_0_MEMORY0_BASE_ADDR					0x058
#define PCI_0_MEMORY0_SIZE						0x060
#define PCI_0_MEMORY1_BASE_ADDR					0x080
#define PCI_0_MEMORY1_SIZE						0x088
#define PCI_0_MEMORY2_BASE_ADDR					0x258
#define PCI_0_MEMORY2_SIZE						0x260
#define PCI_0_MEMORY3_BASE_ADDR					0x280
#define PCI_0_MEMORY3_SIZE						0x288

/* PCI 1 BAR and size registers	 old names of evb64260*/
#define PCI_1I_O_LOW_DECODE_ADDRESS			0x090
#define PCI_1I_O_HIGH_DECODE_ADDRESS			0x098
#define PCI_1MEMORY0_LOW_DECODE_ADDRESS		0x0a0
#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS		0x0a8
#define PCI_1MEMORY1_LOW_DECODE_ADDRESS		0x0b0
#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS		0x0b8
#define PCI_1MEMORY2_LOW_DECODE_ADDRESS		0x2a0
#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS		0x2a8
#define PCI_1MEMORY3_LOW_DECODE_ADDRESS		0x2b0
#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS		0x2b8

/* Make it fit the MV64360 and MV64460 Lowlevel driver */
#define PCI_1_IO_BASE_ADDR						0x090
#define PCI_1_IO_SIZE							0x098
#define PCI_1_MEMORY0_BASE_ADDR					0x0a0
#define PCI_1_MEMORY0_SIZE						0x0a8
#define PCI_1_MEMORY1_BASE_ADDR					0x0b0
#define PCI_1_MEMORY1_SIZE						0x0b8
#define PCI_1_MEMORY2_BASE_ADDR					0x2a0
#define PCI_1_MEMORY2_SIZE						0x2a8
#define PCI_1_MEMORY3_BASE_ADDR					0x2b0
#define PCI_1_MEMORY3_SIZE						0x2b8

/* internal registers space base address */
#define INTERNAL_SPACE_DECODE				0x068
#define INTERNAL_SPACE_BASE_ADDR				INTERNAL_SPACE_DECODE

/* SRAM base address */
#define INTEGRATED_SRAM_BASE_ADDR				0x268

/* Enables the CS , DEV_CS , PCI 0 and PCI 1
   windows above */
#define BASE_ADDR_ENABLE						0x278


#define CPU_0_LOW_DECODE_ADDRESS				0x290
#define CPU_0_HIGH_DECODE_ADDRESS				0x298
#define CPU_1_LOW_DECODE_ADDRESS				0x2c0
#define CPU_1_HIGH_DECODE_ADDRESS				0x2c8

/****************************************/
/* PCI remap registers			*/
/****************************************/
/*****************************************************************************************/
      /* PCI 0 */
/* old fashion evb 64260 */
#define PCI_0I_O_ADDRESS_REMAP				0x0f0
#define PCI_0MEMORY0_ADDRESS_REMAP			0x0f8
#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP		0x320
#define PCI_0MEMORY1_ADDRESS_REMAP			0x100
#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP		0x328
#define PCI_0MEMORY2_ADDRESS_REMAP			0x2f8
#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP		0x330
#define PCI_0MEMORY3_ADDRESS_REMAP			0x300
#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP		0x338

#define PCI_0_IO_ADDR_REMAP						PCI_0I_O_ADDRESS_REMAP
#define PCI_0_MEMORY0_LOW_ADDR_REMAP				PCI_0MEMORY0_ADDRESS_REMAP
#define PCI_0_MEMORY0_HIGH_ADDR_REMAP				PCI_0MEMORY0_HIGH_ADDRESS_REMAP
#define PCI_0_MEMORY1_LOW_ADDR_REMAP				PCI_0MEMORY1_ADDRESS_REMAP
#define PCI_0_MEMORY1_HIGH_ADDR_REMAP				PCI_0MEMORY1_HIGH_ADDRESS_REMAP
#define PCI_0_MEMORY2_LOW_ADDR_REMAP				PCI_0MEMORY2_ADDRESS_REMAP
#define PCI_0_MEMORY2_HIGH_ADDR_REMAP				PCI_0MEMORY2_HIGH_ADDRESS_REMAP
#define PCI_0_MEMORY3_LOW_ADDR_REMAP				PCI_0MEMORY3_ADDRESS_REMAP
#define PCI_0_MEMORY3_HIGH_ADDR_REMAP				PCI_0MEMORY3_HIGH_ADDRESS_REMAP

       /* PCI 1 */
/* old fashion evb 64260 */
#define PCI_1I_O_ADDRESS_REMAP				0x108
#define PCI_1MEMORY0_ADDRESS_REMAP			0x110
#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP		0x340
#define PCI_1MEMORY1_ADDRESS_REMAP			0x118
#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP		0x348
#define PCI_1MEMORY2_ADDRESS_REMAP			0x310
#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP		0x350
#define PCI_1MEMORY3_ADDRESS_REMAP			0x318
#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP		0x358

#define PCI_1_IO_ADDR_REMAP						PCI_1I_O_ADDRESS_REMAP
#define PCI_1_MEMORY0_LOW_ADDR_REMAP				PCI_1MEMORY0_ADDRESS_REMAP
#define PCI_1_MEMORY0_HIGH_ADDR_REMAP				PCI_1MEMORY0_HIGH_ADDRESS_REMAP
#define PCI_1_MEMORY1_LOW_ADDR_REMAP				PCI_1MEMORY1_ADDRESS_REMAP
#define PCI_1_MEMORY1_HIGH_ADDR_REMAP				PCI_1MEMORY1_HIGH_ADDRESS_REMAP
#define PCI_1_MEMORY2_LOW_ADDR_REMAP				PCI_1MEMORY2_ADDRESS_REMAP
#define PCI_1_MEMORY2_HIGH_ADDR_REMAP				PCI_1MEMORY2_HIGH_ADDRESS_REMAP
#define PCI_1_MEMORY3_LOW_ADDR_REMAP				PCI_1MEMORY3_ADDRESS_REMAP
#define PCI_1_MEMORY3_HIGH_ADDR_REMAP				PCI_1MEMORY3_HIGH_ADDRESS_REMAP

/* old fashion evb 64260 */
#define CPU_PCI_0_HEADERS_RETARGET_CONTROL			0x3b0
#define CPU_PCI_0_HEADERS_RETARGET_BASE				0x3b8
#define CPU_PCI_1_HEADERS_RETARGET_CONTROL			0x3c0
#define CPU_PCI_1_HEADERS_RETARGET_BASE				0x3c8
#define CPU_GE_HEADERS_RETARGET_CONTROL				0x3d0
#define CPU_GE_HEADERS_RETARGET_BASE				0x3d8

/* MV64360 and MV64460 no changes needed*/
/*****************************************************************************************/

/****************************************/
/*	   CPU Control Registers	*/
/****************************************/
/* CPU MASTER CONTROL REGISTER */
#define CPU_CONFIGURATION				0x000
#define CPU_MASTER_CONTROL				0x160

#define CPU_CONFIG							0x000
#define CPU_MODE							0x120
#define CPU_MASTER_CONTROL						0x160
/* new in MV64360 and MV64460 */
#define CPU_CROSS_BAR_CONTROL_LOW				0x150
#define CPU_CROSS_BAR_CONTROL_HIGH				0x158
#define CPU_CROSS_BAR_TIMEOUT					0x168

/****************************************/
/* SMP RegisterS			*/
/****************************************/

#define SMP_WHO_AM_I							0x200
#define SMP_CPU0_DOORBELL						0x214
#define SMP_CPU0_DOORBELL_CLEAR					0x21C
#define SMP_CPU1_DOORBELL						0x224
#define SMP_CPU1_DOORBELL_CLEAR					0x22C
#define SMP_CPU0_DOORBELL_MASK					0x234
#define SMP_CPU1_DOORBELL_MASK					0x23C
#define SMP_SEMAPHOR0							0x244
#define SMP_SEMAPHOR1							0x24c
#define SMP_SEMAPHOR2							0x254
#define SMP_SEMAPHOR3							0x25c
#define SMP_SEMAPHOR4							0x264
#define SMP_SEMAPHOR5							0x26c
#define SMP_SEMAPHOR6							0x274
#define SMP_SEMAPHOR7							0x27c


/****************************************/
/* CPU Sync Barrier				*/
/****************************************/
#define CPU_0_SYNC_BARRIER_TRIGGER				0x0c0
#define CPU_0_SYNC_BARRIER_VIRTUAL				0x0c8
#define CPU_1_SYNC_BARRIER_TRIGGER				0x0d0
#define CPU_1_SYNC_BARRIER_VIRTUAL				0x0d8


/****************************************/
/* CPU Access Protect			*/
/****************************************/

#define CPU_LOW_PROTECT_ADDRESS_0			    0x180
#define CPU_HIGH_PROTECT_ADDRESS_0			    0x188
#define CPU_LOW_PROTECT_ADDRESS_1			    0x190
#define CPU_HIGH_PROTECT_ADDRESS_1			    0x198
#define CPU_LOW_PROTECT_ADDRESS_2			    0x1a0
#define CPU_HIGH_PROTECT_ADDRESS_2			    0x1a8
#define CPU_LOW_PROTECT_ADDRESS_3			    0x1b0
#define CPU_HIGH_PROTECT_ADDRESS_3			    0x1b8
/*#define CPU_LOW_PROTECT_ADDRESS_4			      0x1c0
#define CPU_HIGH_PROTECT_ADDRESS_4			    0x1c8
#define CPU_LOW_PROTECT_ADDRESS_5			    0x1d0
#define CPU_HIGH_PROTECT_ADDRESS_5			    0x1d8
#define CPU_LOW_PROTECT_ADDRESS_6			    0x1e0
#define CPU_HIGH_PROTECT_ADDRESS_6			    0x1e8
#define CPU_LOW_PROTECT_ADDRESS_7			    0x1f0
#define CPU_HIGH_PROTECT_ADDRESS_7			    0x1f8
*/

#define CPU_PROTECT_WINDOW_0_BASE_ADDR		     CPU_LOW_PROTECT_ADDRESS_0 /* 0x180 */
#define CPU_PROTECT_WINDOW_0_SIZE			    CPU_HIGH_PROTECT_ADDRESS_0 /* 0x188 */