sdram_init.c
来自「适合KS8695X」· C语言 代码 · 共 1,684 行 · 第 1/4 页
C
1,684 行
case 22: /* Suported AutoPreCharge */
DP (printf ("\nModul Attributes (SPD Byte 22): \n"));
dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
dimmInfo->suportedAutoPreCharge =
(data[i] & BIT1) >> 1;
dimmInfo->suportedPreChargeAll =
(data[i] & BIT2) >> 2;
dimmInfo->suportedWrite1ReadBurst =
(data[i] & BIT3) >> 3;
dimmInfo->suported5PercentLowVCC =
(data[i] & BIT4) >> 4;
dimmInfo->suported5PercentUpperVCC =
(data[i] & BIT5) >> 5;
#ifdef DEBUG
if (dimmInfo->suportedEarlyRasPreCharge == 1)
DP (printf
(" - Early Ras Precharge: Yes \n"));
else
DP (printf
(" - Early Ras Precharge: No \n"));
if (dimmInfo->suportedAutoPreCharge == 1)
DP (printf
(" - AutoPreCharge: Yes \n"));
else
DP (printf
(" - AutoPreCharge: No \n"));
if (dimmInfo->suportedPreChargeAll == 1)
DP (printf
(" - Precharge All: Yes \n"));
else
DP (printf
(" - Precharge All: No \n"));
if (dimmInfo->suportedWrite1ReadBurst == 1)
DP (printf
(" - Write 1/ReadBurst: Yes \n"));
else
DP (printf
(" - Write 1/ReadBurst: No \n"));
if (dimmInfo->suported5PercentLowVCC == 1)
DP (printf
(" - lower VCC tolerance: 5 Percent \n"));
else
DP (printf
(" - lower VCC tolerance: 10 Percent \n"));
if (dimmInfo->suported5PercentUpperVCC == 1)
DP (printf
(" - upper VCC tolerance: 5 Percent \n"));
else
DP (printf
(" - upper VCC tolerance: 10 Percent \n"));
#endif
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
maskLeftOfPoint =
(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
maskRightOfPoint =
(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
rightOfPoint = (data[i] & maskRightOfPoint) * mult;
dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
leftOfPoint;
dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
rightOfPoint;
DP (printf
("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
leftOfPoint, rightOfPoint));
/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 24: /* Clock To Data Out 2nd highest Cas Latency Value */
div = (dimmInfo->memoryType == DDR) ? 100 : 10;
time_tmp =
(((data[i] & 0xf0) >> 4) * 10) +
((data[i] & 0x0f));
leftOfPoint = time_tmp / div;
rightOfPoint = time_tmp % div;
dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
DP (printf
("Clock To Data Out (2nd CL value): %d.%2d [ns]\n",
leftOfPoint, rightOfPoint));
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
maskLeftOfPoint =
(dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
maskRightOfPoint =
(dimmInfo->memoryType == DDR) ? 0xf : 0x03;
leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
rightOfPoint = (data[i] & maskRightOfPoint) * mult;
dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
leftOfPoint;
dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
rightOfPoint;
DP (printf
("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
leftOfPoint, rightOfPoint));
/*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 26: /* Clock To Data Out 3rd highest Cas Latency Value */
div = (dimmInfo->memoryType == DDR) ? 100 : 10;
time_tmp =
(((data[i] & 0xf0) >> 4) * 10) +
((data[i] & 0x0f));
leftOfPoint = time_tmp / div;
rightOfPoint = time_tmp % div;
dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
DP (printf
("Clock To Data Out (3rd CL value): %d.%2d [ns]\n",
leftOfPoint, rightOfPoint));
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 27: /* Minimum Row Precharge Time */
shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
maskLeftOfPoint =
(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
maskRightOfPoint =
(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
rightOfPoint = (data[i] & maskRightOfPoint) * 25;
dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint); /* measured in n times 10ps Intervals */
trp_clocks =
(dimmInfo->minRowPrechargeTime +
(tmemclk - 1)) / tmemclk;
DP (printf
("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n",
tmemclk, tmemclk / 100, tmemclk % 100));
DP (printf
("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n",
leftOfPoint, rightOfPoint, trp_clocks));
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 28: /* Minimum Row Active to Row Active Time */
shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
maskLeftOfPoint =
(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
maskRightOfPoint =
(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
rightOfPoint = (data[i] & maskRightOfPoint) * 25;
dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
trrd_clocks =
(dimmInfo->minRowActiveRowActiveDelay +
(tmemclk - 1)) / tmemclk;
DP (printf
("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n",
leftOfPoint, rightOfPoint, trp_clocks));
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 29: /* Minimum Ras-To-Cas Delay */
shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
maskLeftOfPoint =
(dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
maskRightOfPoint =
(dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
rightOfPoint = (data[i] & maskRightOfPoint) * 25;
dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
trcd_clocks =
(dimmInfo->minRowActiveRowActiveDelay +
(tmemclk - 1)) / tmemclk;
DP (printf
("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n",
leftOfPoint, rightOfPoint, trp_clocks));
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 30: /* Minimum Ras Pulse Width */
dimmInfo->minRasPulseWidth = data[i];
tras_clocks =
(NSto10PS (data[i]) +
(tmemclk - 1)) / tmemclk;
DP (printf
("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n",
dimmInfo->minRasPulseWidth, tras_clocks));
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 31: /* Module Bank Density */
dimmInfo->moduleBankDensity = data[i];
DP (printf
("Module Bank Density: %d\n",
dimmInfo->moduleBankDensity));
#ifdef DEBUG
DP (printf
("*** Offered Densities (more than 1 = Multisize-Module): "));
{
if (dimmInfo->moduleBankDensity & 1)
DP (printf ("4MB, "));
if (dimmInfo->moduleBankDensity & 2)
DP (printf ("8MB, "));
if (dimmInfo->moduleBankDensity & 4)
DP (printf ("16MB, "));
if (dimmInfo->moduleBankDensity & 8)
DP (printf ("32MB, "));
if (dimmInfo->moduleBankDensity & 16)
DP (printf ("64MB, "));
if (dimmInfo->moduleBankDensity & 32)
DP (printf ("128MB, "));
if ((dimmInfo->moduleBankDensity & 64)
|| (dimmInfo->moduleBankDensity & 128)) {
DP (printf ("ERROR, "));
hang ();
}
}
DP (printf ("\n"));
#endif
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 32: /* Address And Command Setup Time (measured in ns/1000) */
sign = 1;
switch (dimmInfo->memoryType) {
case DDR:
time_tmp =
(((data[i] & 0xf0) >> 4) * 10) +
((data[i] & 0x0f));
leftOfPoint = time_tmp / 100;
rightOfPoint = time_tmp % 100;
break;
case SDRAM:
leftOfPoint = (data[i] & 0xf0) >> 4;
if (leftOfPoint > 7) {
leftOfPoint = data[i] & 0x70 >> 4;
sign = -1;
}
rightOfPoint = (data[i] & 0x0f);
break;
}
dimmInfo->addrAndCommandSetupTime =
(leftOfPoint * 100 + rightOfPoint) * sign;
DP (printf
("Address And Command Setup Time [ns]: %d.%d\n",
sign * leftOfPoint, rightOfPoint));
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 33: /* Address And Command Hold Time */
sign = 1;
switch (dimmInfo->memoryType) {
case DDR:
time_tmp =
(((data[i] & 0xf0) >> 4) * 10) +
((data[i] & 0x0f));
leftOfPoint = time_tmp / 100;
rightOfPoint = time_tmp % 100;
break;
case SDRAM:
leftOfPoint = (data[i] & 0xf0) >> 4;
if (leftOfPoint > 7) {
leftOfPoint = data[i] & 0x70 >> 4;
sign = -1;
}
rightOfPoint = (data[i] & 0x0f);
break;
}
dimmInfo->addrAndCommandHoldTime =
(leftOfPoint * 100 + rightOfPoint) * sign;
DP (printf
("Address And Command Hold Time [ns]: %d.%d\n",
sign * leftOfPoint, rightOfPoint));
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 34: /* Data Input Setup Time */
sign = 1;
switch (dimmInfo->memoryType) {
case DDR:
time_tmp =
(((data[i] & 0xf0) >> 4) * 10) +
((data[i] & 0x0f));
leftOfPoint = time_tmp / 100;
rightOfPoint = time_tmp % 100;
break;
case SDRAM:
leftOfPoint = (data[i] & 0xf0) >> 4;
if (leftOfPoint > 7) {
leftOfPoint = data[i] & 0x70 >> 4;
sign = -1;
}
rightOfPoint = (data[i] & 0x0f);
break;
}
dimmInfo->dataInputSetupTime =
(leftOfPoint * 100 + rightOfPoint) * sign;
DP (printf
("Data Input Setup Time [ns]: %d.%d\n",
sign * leftOfPoint, rightOfPoint));
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
case 35: /* Data Input Hold Time */
sign = 1;
switch (dimmInfo->memoryType) {
case DDR:
time_tmp =
(((data[i] & 0xf0) >> 4) * 10) +
((data[i] & 0x0f));
leftOfPoint = time_tmp / 100;
rightOfPoint = time_tmp % 100;
break;
case SDRAM:
leftOfPoint = (data[i] & 0xf0) >> 4;
if (leftOfPoint > 7) {
leftOfPoint = data[i] & 0x70 >> 4;
sign = -1;
}
rightOfPoint = (data[i] & 0x0f);
break;
}
dimmInfo->dataInputHoldTime =
(leftOfPoint * 100 + rightOfPoint) * sign;
DP (printf
("Data Input Hold Time [ns]: %d.%d\n\n",
sign * leftOfPoint, rightOfPoint));
break;
/*------------------------------------------------------------------------------------------------------------------------------*/
}
}
/* calculating the sdram density */
for (i = 0;
i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
i++) {
density = density * 2;
}
dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
dimmInfo->sdramWidth;
dimmInfo->numberOfDevices =
(dimmInfo->dataWidth / dimmInfo->sdramWidth) *
dimmInfo->numOfModuleBanks;
devicesForErrCheck =
(dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth;
if ((dimmInfo->errorCheckType == 0x1)
|| (dimmInfo->errorCheckType == 0x2)
|| (dimmInfo->errorCheckType == 0x3)) {
dimmInfo->size =
(dimmInfo->deviceDensity / 8) *
(dimmInfo->numberOfDevices - devicesForErrCheck);
} else {
dimmInfo->size =
(dimmInfo->deviceDensity / 8) *
dimmInfo->numberOfDevices;
}
/* compute the module DRB size */
tmp = (1 <<
(dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
tmp *= dimmInfo->numOfModuleBanks;
tmp *= dimmInfo->sdramWidth;
tmp = tmp >> 24; /* div by 0x4000000 (64M) */
dimmInfo->drb_size = (uchar) tmp;
DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size));
/* try a CAS latency of 3 first... */
/* bit 1 is CL2, bit 2 is CL3 */
supp_cal = (dimmInfo->suportedCasLatencies & 0x1c) >> 1;
cal_val = 0;
if (supp_cal & 8) {
if (NS10to10PS (data[9]) <= tmemclk)
cal_val = 6;
}
if (supp_cal & 4) {
if (NS10to10PS (data[9]) <= tmemclk)
cal_val = 5;
}
/* then 2... */
if (supp_cal & 2) {
if (NS10to10PS (data[23]) <= tmemclk)
cal_val = 4;
}
DP (printf ("cal_val = %d\n", cal_val * 5));
/* bummer, did't work... */
if (cal_val == 0) {
DP (printf ("Couldn't find a good CAS latency\n"));
hang ();
return 0;
}
return true;
}
/* sets up the GT properly with information passed in */
int setup_sdram (AUX_MEM_DIMM_INFO * info)
{
ulong tmp, check;
ulong tmp_sdram_mode = 0; /* 0x141c */
ulong tmp_dunit_control_low = 0; /* 0x1404 */
int i;
/* sanity checking */
if (!info->numOfModuleBanks) {
printf ("setup_sdram called with 0 banks\n");
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