cmd_pci405.c

来自「适合KS8695X」· C语言 代码 · 共 986 行 · 第 1/2 页

C
986 行
字号
12
{
	unsigned int addr;
	unsigned int size;
	unsigned int countmax;
	int max;
	volatile unsigned long *ptr;
	volatile unsigned long val;
	int loopcount = 0;

	addr = simple_strtol (argv[1], NULL, 16);
	size = simple_strtol (argv[2], NULL, 16);
	countmax = simple_strtol (argv[3], NULL, 16);
	if (countmax == 0)
		countmax = 1000;

	do_getplb(NULL, 0, 0, NULL);

#if 0
	out32r(PMM0LA, 0);
	out32r(PMM0PCILA, 0);
	out32r(PMM0PCIHA, 0);
	out32r(PMM0MA, 0);
	out32r(PMM1LA, PCI_ADDR);
	out32r(PMM1PCILA, addr & 0xff000000);
	out32r(PMM1PCIHA, 0x00000000);
	out32r(PMM1MA, 0xff000001);
#endif

	printf("PMM1LA    =%08lx\n", in32r(PMM1LA));
	printf("PMM1MA    =%08lx\n", in32r(PMM1MA));
	printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA));
	printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA));

	addr = PCI_ADDR | (addr & 0x00ffffff);
	printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax);

	max = size >> 2;

	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */

	while (1) {

		/*
		 * Write one values to host via pci busmastering
		 */
		ptr = (volatile unsigned long *)addr;
		*ptr = 0x01234567;

		/*
		 * Read one value back
		 */
		ptr = (volatile unsigned long *)addr;
		val = *ptr;

		/*
		 * One pci config write
		 */
/*		pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); */
/*		ibmPciConfigWrite(0x44, 1, 0x00); */
		ibmPciConfigWrite(0x2e, 2, 0x1234); /* subsystem id */

		if (loopcount++ > countmax) {
			/* Abort if ctrl-c was pressed */
			if (ctrlc()) {
				puts("\nAbort\n");
				return 0;
			}

			putc('.');

			loopcount = 0;
		}
	}

	return 0;
}
U_BOOT_CMD(
	writepci2,	4,	1,	do_writepci2,
	"writepci2- Write some data to pcibus\n",
	"<addr> <size>\n"
	"        - Write some data to pcibus.\n"
);

int do_writepci22(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	unsigned int addr;
	unsigned int size;
	unsigned int countmax = 0;
	volatile unsigned long *ptr;
	volatile unsigned long val;

	addr = simple_strtol (argv[1], NULL, 16);
	size = simple_strtol (argv[2], NULL, 16);

	addr = PCI_ADDR | (addr & 0x00ffffff);
	printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax);
	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */

	while (1) {

		/*
		 * Write one values to host via pci busmastering
		 */
		ptr = (volatile unsigned long *)addr;
		*ptr = 0x01234567;

		/*
		 * Read one value back
		 */
		ptr = (volatile unsigned long *)addr;
		val = *ptr;

		/*
		 * One pci config write
		 */
		ibmPciConfigWrite(0x2e, 2, 0x1234); /* subsystem id */
	}

	return 0;
}
U_BOOT_CMD(
	writepci22,	4,	1,	do_writepci22,
	"writepci22- Write some data to pcibus\n",
	"<addr> <size>\n"
	"        - Write some data to pcibus.\n"
);

int ibmPciConfigWrite3
(
	int offset,     /* offset into the configuration space */
	int width,      /* data width                          */
	unsigned int data       /* data to be written                  */
	)
{
	/*
	 * Write config register address to the PCI config address register
	 * bit 31 must be 1 and bits 1:0 must be 0 (note LE bit notation)
	 */
	out32r(PCI_CFGADDR, 0x80000000 | (offset & 0xFFFFFFFC));

#if 1 /* test-only */
	ppcSync();
#endif

	/*
	 * Write value to be written to the PCI config data register
	 */
	switch ( width ) {
	case 1: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned char)(data & 0xFF));
		break;
	case 2: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned short)(data & 0xFFFF));
		break;
	case 4:	out32r(PCI_CFGDATA | (offset & 0x3), data);
		break;
	}

	return (0);
}

int do_writepci3(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	unsigned int addr;
	unsigned int size;
	unsigned int countmax;
	int max;
	volatile unsigned long *ptr;
	volatile unsigned long val;
	int loopcount = 0;

	addr = simple_strtol (argv[1], NULL, 16);
	size = simple_strtol (argv[2], NULL, 16);
	countmax = simple_strtol (argv[3], NULL, 16);
	if (countmax == 0)
		countmax = 1000;

	do_getplb(NULL, 0, 0, NULL);

#if 0
	out32r(PMM0LA, 0);
	out32r(PMM0PCILA, 0);
	out32r(PMM0PCIHA, 0);
	out32r(PMM0MA, 0);
	out32r(PMM1LA, PCI_ADDR);
	out32r(PMM1PCILA, addr & 0xff000000);
	out32r(PMM1PCIHA, 0x00000000);
	out32r(PMM1MA, 0xff000001);
#endif

	printf("PMM1LA    =%08lx\n", in32r(PMM1LA));
	printf("PMM1MA    =%08lx\n", in32r(PMM1MA));
	printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA));
	printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA));

	addr = PCI_ADDR | (addr & 0x00ffffff);
	printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax);

	max = size >> 2;

	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */

	while (1) {

		/*
		 * Write one values to host via pci busmastering
		 */
		ptr = (volatile unsigned long *)addr;
		*ptr = 0x01234567;

		/*
		 * Read one value back
		 */
		ptr = (volatile unsigned long *)addr;
		val = *ptr;

		/*
		 * One pci config write
		 */
/*		pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); */
/*		ibmPciConfigWrite(0x44, 1, 0x00); */
		ibmPciConfigWrite3(0x2e, 2, 0x1234); /* subsystem id */

		if (loopcount++ > countmax) {
			/* Abort if ctrl-c was pressed */
			if (ctrlc()) {
				puts("\nAbort\n");
				return 0;
			}

			putc('.');

			loopcount = 0;
		}
	}

	return 0;
}
U_BOOT_CMD(
	writepci3,	4,	1,	do_writepci3,
	"writepci3- Write some data to pcibus\n",
	"<addr> <size>\n"
	"        - Write some data to pcibus.\n"
);


#define SECTOR_SIZE 	32		/* 32 byte cache line */
#define SECTOR_MASK	0x1F

void my_flush_dcache(ulong lcl_addr, ulong count)
{
  unsigned int lcl_target;

  /* promote to nearest cache sector */
  lcl_target =  (lcl_addr + count + SECTOR_SIZE - 1) & ~SECTOR_MASK;
  lcl_addr &= ~SECTOR_MASK;
  while (lcl_addr != lcl_target)
    {
      /*      ppcDcbf((void *)lcl_addr);*/
      __asm__("dcbf 0,%0": :"r" (lcl_addr));
      lcl_addr += SECTOR_SIZE;
    }
  __asm__("sync");		/* Always flush prefetch queue in any case */
}

int do_writepci_cache(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	unsigned int addr;
	unsigned int size;
	unsigned int countmax;
	int i;
	volatile unsigned long *ptr;
	volatile unsigned long val;
	int loopcount = 0;

	addr = simple_strtol (argv[1], NULL, 16);
	size = simple_strtol (argv[2], NULL, 16);
	countmax = simple_strtol (argv[3], NULL, 16);
	if (countmax == 0)
		countmax = 1000;

	do_getplb(NULL, 0, 0, NULL);

#if 0
	out32r(PMM0LA, 0);
	out32r(PMM0PCILA, 0);
	out32r(PMM0PCIHA, 0);
	out32r(PMM0MA, 0);
	out32r(PMM1LA, PCI_ADDR);
	out32r(PMM1PCILA, addr & 0xff000000);
	out32r(PMM1PCIHA, 0x00000000);
	out32r(PMM1MA, 0xff000001);
#endif

	printf("PMM1LA    =%08lx\n", in32r(PMM1LA));
	printf("PMM1MA    =%08lx\n", in32r(PMM1MA));
	printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA));
	printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA));

	addr = PCI_ADDR | (addr & 0x00ffffff);
	printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax);

	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */

	i = 0;

	/*
	 * Set pci region as cachable
	 */
	ppcSync();
	__asm__ volatile ("	addis	4,0,0x0000 ");
	__asm__ volatile ("	addi	4,4,0x0080 ");
	__asm__ volatile ("	mtdccr	4 ");
	ppcSync();

	while (1) {

		/*
		 * Write one values to host via pci busmastering
		 */
		ptr = (volatile unsigned long *)addr;
		printf("A\n"); /* test-only */
		*ptr++ = i++;
		*ptr++ = i++;
		*ptr++ = i++;
		*ptr++ = i++;
		*ptr++ = i++;
		*ptr++ = i++;
		*ptr++ = i++;
		*ptr++ = i++;
		printf("B\n"); /* test-only */
		my_flush_dcache(addr, 32);
		printf("C\n"); /* test-only */

		/*
		 * Read one value back
		 */
		ptr = (volatile unsigned long *)addr;
		val = *ptr;
		printf("D\n"); /* test-only */

		/*
		 * One pci config write
		 */
/*		pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); */
/*		ibmPciConfigWrite(0x44, 1, 0x00); */
		ibmPciConfigWrite3(0x2e, 2, 0x1234); /* subsystem id */
		printf("E\n"); /* test-only */

		if (loopcount++ > countmax) {
			/* Abort if ctrl-c was pressed */
			if (ctrlc()) {
				puts("\nAbort\n");
				return 0;
			}

			putc('.');

			loopcount = 0;
		}
	}

	return 0;
}
U_BOOT_CMD(
	writepci_cache,	4,	1,	do_writepci_cache,
	"writepci_cache - Write some data to pcibus\n",
	"<addr> <size>\n"
	"        - Write some data to pcibus.\n"
);

int do_savepci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	unsigned int *ptr;
	int i;

	/*
	 * Save own pci configuration in PRAM
	 */
	memset((char *)PCI_REGS_ADDR, 0, PCI_REGS_LEN);
	ptr = (unsigned int *)PCI_REGS_ADDR + 1;
	for (i=0; i<0x40; i+=4) {
		pci_read_config_dword(PCIDEVID_405GP, i, ptr++);
	}
	ptr = (unsigned int *)PCI_REGS_ADDR;
	*ptr = crc32(0, (char *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4);

	printf("\nStoring PCI Configuration Regs...\n");

	return 0;
}
U_BOOT_CMD(
	savepci,	4,	1,	do_savepci,
	"savepci  - Save all pci regs\n",
	"<addr> <size>\n"
	"        - Write some data to pcibus.\n"
);

int do_restorepci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	unsigned int *ptr;
	int i;

	/*
	 * Rewrite pci config regs (only after soft-reset with magic set)
	 */
	ptr = (unsigned int *)PCI_REGS_ADDR;
	if (crc32(0, (char *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
		puts("Restoring PCI Configurations Regs!\n");
		ptr = (unsigned int *)PCI_REGS_ADDR + 1;
		for (i=0; i<0x40; i+=4) {
			pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
		}
	}
	mtdcr(uicsr, 0xFFFFFFFF);        /* clear all ints */

	return 0;
}
U_BOOT_CMD(
	restorepci,	4,	1,	do_restorepci,
	"restorepci  - Restore all pci regs\n",
	"<addr> <size>\n"
	"        - Write some data to pcibus.\n"
);


extern void write_without_sync(void);
extern void write_with_sync(void);
extern void write_with_less_sync(void);
extern void write_with_more_sync(void);

/*
 * code from IBM-PPCSUPP
 */
int do_writeibm1(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */

	write_without_sync();

	return 0;
}
U_BOOT_CMD(
	writeibm1,	4,	1,	do_writeibm1,
	"writeibm1- Write some data to pcibus (without sync)\n",
	"<addr> <size>\n"
	"        - Write some data to pcibus.\n"
);

int do_writeibm2(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */

	write_with_sync();

	return 0;
}
U_BOOT_CMD(
	writeibm2,	4,	1,	do_writeibm2,
	"writeibm2- Write some data to pcibus (with sync)\n",
	"<addr> <size>\n"
	"        - Write some data to pcibus.\n"
);

int do_writeibm22(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */

	write_with_less_sync();

	return 0;
}
U_BOOT_CMD(
	writeibm22,	4,	1,	do_writeibm22,
	"writeibm22- Write some data to pcibus (with less sync)\n",
	"<addr> <size>\n"
	"        - Write some data to pcibus.\n"
);

int do_writeibm3(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */

	write_with_more_sync();

	return 0;
}
U_BOOT_CMD(
	writeibm3,	4,	1,	do_writeibm3,
	"writeibm3- Write some data to pcibus (with more sync)\n",
	"<addr> <size>\n"
	"        - Write some data to pcibus.\n"
);
#endif
12

cmd_pci405.c - 源码说明

本页面展示了「适合KS8695X」中的 cmd_pci405.c 源码文件，采用 C语言 编程语言编写，共 986 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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