at91rm9200.h
来自「适合KS8695X」· C头文件 代码 · 共 736 行 · 第 1/4 页
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AT91_REG DBGU_MR; /* Mode Register */
AT91_REG DBGU_IER; /* Interrupt Enable Register */
AT91_REG DBGU_IDR; /* Interrupt Disable Register */
AT91_REG DBGU_IMR; /* Interrupt Mask Register */
AT91_REG DBGU_CSR; /* Channel Status Register */
AT91_REG DBGU_RHR; /* Receiver Holding Register */
AT91_REG DBGU_THR; /* Transmitter Holding Register */
AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */
AT91_REG Reserved0[7]; /* */
AT91_REG DBGU_C1R; /* Chip ID1 Register */
AT91_REG DBGU_C2R; /* Chip ID2 Register */
AT91_REG DBGU_FNTR; /* Force NTRST Register */
AT91_REG Reserved1[45]; /* */
AT91_REG DBGU_RPR; /* Receive Pointer Register */
AT91_REG DBGU_RCR; /* Receive Counter Register */
AT91_REG DBGU_TPR; /* Transmit Pointer Register */
AT91_REG DBGU_TCR; /* Transmit Counter Register */
AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */
AT91_REG DBGU_RNCR; /* Receive Next Counter Register */
AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */
AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */
AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */
AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */
} AT91S_DBGU, *AT91PS_DBGU;
/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* (DBGU) RXRDY Interrupt */
#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* (DBGU) TXRDY Interrupt */
#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) /* (DBGU) End of Receive Transfer Interrupt */
#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) /* (DBGU) End of Transmit Interrupt */
#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) /* (DBGU) Overrun Interrupt */
#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) /* (DBGU) Framing Error Interrupt */
#define AT91C_US_PARE ((unsigned int) 0x1 << 7) /* (DBGU) Parity Error Interrupt */
#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) /* (DBGU) TXEMPTY Interrupt */
#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt */
#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt */
#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt */
#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt */
/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* (DBGU) Reset Receiver */
#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* (DBGU) Reset Transmitter */
#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* (DBGU) Receiver Enable */
#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* (DBGU) Receiver Disable */
#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* (DBGU) Transmitter Enable */
#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* (DBGU) Transmitter Disable */
#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* (USART) Clock */
#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* (USART) Character Length: 8 bits */
#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */
#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */
/* ***************************************************************************** */
/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */
/* ***************************************************************************** */
typedef struct _AT91S_SMC2 {
AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */
} AT91S_SMC2, *AT91PS_SMC2;
/* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- */
#define AT91C_SMC2_NWS ((unsigned int) 0x7F << 0) /* (SMC2) Number of Wait States */
#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */
#define AT91C_SMC2_TDF ((unsigned int) 0xF << 8) /* (SMC2) Data Float Time */
#define AT91C_SMC2_BAT ((unsigned int) 0x1 << 12) /* (SMC2) Byte Access Type */
#define AT91C_SMC2_DBW ((unsigned int) 0x1 << 13) /* (SMC2) Data Bus Width */
#define AT91C_SMC2_DBW_16 ((unsigned int) 0x1 << 13) /* (SMC2) 16-bit. */
#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
#define AT91C_SMC2_DRP ((unsigned int) 0x1 << 15) /* (SMC2) Data Read Protocol */
#define AT91C_SMC2_ACSS ((unsigned int) 0x3 << 16) /* (SMC2) Address to Chip Select Setup */
#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */
#define AT91C_SMC2_ACSS_1_CYCLE ((unsigned int) 0x1 << 16) /* (SMC2) One cycle less at the beginning and the end of the access. */
#define AT91C_SMC2_ACSS_2_CYCLES ((unsigned int) 0x2 << 16) /* (SMC2) Two cycles less at the beginning and the end of the access. */
#define AT91C_SMC2_ACSS_3_CYCLES ((unsigned int) 0x3 << 16) /* (SMC2) Three cycles less at the beginning and the end of the access. */
#define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */
#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */
/* ***************************************************************************** */
/* SOFTWARE API DEFINITION FOR Power Management Controler */
/* ******************************************************************************/
typedef struct _AT91S_PMC {
AT91_REG PMC_SCER; /* System Clock Enable Register */
AT91_REG PMC_SCDR; /* System Clock Disable Register */
AT91_REG PMC_SCSR; /* System Clock Status Register */
AT91_REG Reserved0[1]; /* */
AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */
AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */
AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */
AT91_REG Reserved1[5]; /* */
AT91_REG PMC_MCKR; /* Master Clock Register */
AT91_REG Reserved2[3]; /* */
AT91_REG PMC_PCKR[8]; /* Programmable Clock Register */
AT91_REG PMC_IER; /* Interrupt Enable Register */
AT91_REG PMC_IDR; /* Interrupt Disable Register */
AT91_REG PMC_SR; /* Status Register */
AT91_REG PMC_IMR; /* Interrupt Mask Register */
} AT91S_PMC, *AT91PS_PMC;
/*------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/
#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) /* (PMC) Processor Clock */
#define AT91C_PMC_UDP ((unsigned int) 0x1 << 1) /* (PMC) USB Device Port Clock */
#define AT91C_PMC_MCKUDP ((unsigned int) 0x1 << 2) /* (PMC) USB Device Port Master Clock Automatic Disable on Suspend */
#define AT91C_PMC_UHP ((unsigned int) 0x1 << 4) /* (PMC) USB Host Port Clock */
#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) /* (PMC) Programmable Clock Output */
#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) /* (PMC) Programmable Clock Output */
#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) /* (PMC) Programmable Clock Output */
#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) /* (PMC) Programmable Clock Output */
#define AT91C_PMC_PCK4 ((unsigned int) 0x1 << 12) /* (PMC) Programmable Clock Output */
#define AT91C_PMC_PCK5 ((unsigned int) 0x1 << 13) /* (PMC) Programmable Clock Output */
#define AT91C_PMC_PCK6 ((unsigned int) 0x1 << 14) /* (PMC) Programmable Clock Output */
#define AT91C_PMC_PCK7 ((unsigned int) 0x1 << 15) /* (PMC) Programmable Clock Output */
/*-------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register ------*/
/*-------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------*/
/*-------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------*/
#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) /* (PMC) Programmable Clock Selection */
#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) /* (PMC) Slow Clock is selected */
#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) /* (PMC) Main Clock is selected */
#define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) /* (PMC) Clock from PLL A is selected */
#define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) /* (PMC) Clock from PLL B is selected */
#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) /* (PMC) Programmable Clock Prescaler */
#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) /* (PMC) Selected clock */
#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) /* (PMC) Selected clock divided by 2 */
#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) /* (PMC) Selected clock divided by 4 */
#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) /* (PMC) Selected clock divided by 8 */
#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) /* (PMC) Selected clock divided by 16 */
#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) /* (PMC) Selected clock divided by 32 */
#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) /* (PMC) Selected clock divided by 64 */
#define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) /* (PMC) Master Clock Division */
#define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) /* (PMC) The master clock and the processor clock are the same */
#define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) /* (PMC) The processor clock is twice as fast as the master clock */
#define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) /* (PMC) The processor clock is three times faster than the master clock */
#define AT91C_PMC_MDIV_4 ((unsigned int) 0x3 << 8) /* (PMC) The processor clock is four times faster than the master clock */
/*------ PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------*/
/*------ PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------*/
#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) /* (PMC) MOSC Status/Enable/Disable/Mask */
#define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) /* (PMC) PLL A Status/Enable/Disable/Mask */
#define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) /* (PMC) PLL B Status/Enable/Disable/Mask */
#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
#define AT91C_PMC_PCK4RDY ((unsigned int) 0x1 << 12) /* (PMC) PCK4_RDY Status/Enable/Disable/Mask */
#define AT91C_PMC_PCK5RDY ((unsigned int) 0x1 << 13) /* (PMC) PCK5_RDY Status/Enable/Disable/Mask */
#define AT91C_PMC_PCK6RDY ((unsigned int) 0x1 << 14) /* (PMC) PCK6_RDY Status/Enable/Disable/Mask */
#define AT91C_PMC_PCK7RDY ((unsigned int) 0x1 << 15) /* (PMC) PCK7_RDY Status/Enable/Disable/Mask */
/*---- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------*/
/*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/
/*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/
/* ***************************************************************************** */
/* SOFTWARE API DEFINITION FOR Ethernet MAC */
/* ***************************************************************************** */
typedef struct _AT91S_EMAC {
AT91_REG EMAC_CTL; /* Network Control Register */
AT91_REG EMAC_CFG; /* Network Configuration Register */
AT91_REG EMAC_SR; /* Network Status Register */
AT91_REG EMAC_TAR; /* Transmit Address Register */
AT91_REG EMAC_TCR; /* Transmit Control Register */
AT91_REG EMAC_TSR; /* Transmit Status Register */
AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */
AT91_REG Reserved0[1]; /* */
AT91_REG EMAC_RSR; /* Receive Status Register */
AT91_REG EMAC_ISR; /* Interrupt Status Register */
AT91_REG EMAC_IER; /* Interrupt Enable Register */
AT91_REG EMAC_IDR; /* Interrupt Disable Register */
AT91_REG EMAC_IMR; /* Interrupt Mask Register */
AT91_REG EMAC_MAN; /* PHY Maintenance Register */
AT91_REG Reserved1[2]; /* */
AT91_REG EMAC_FRA; /* Frames Transmitted OK Register */
AT91_REG EMAC_SCOL; /* Single Collision Frame Register */
AT91_REG EMAC_MCOL; /* Multiple Collision Frame Register */
AT91_REG EMAC_OK; /* Frames Received OK Register */
AT91_REG EMAC_SEQE; /* Frame Check Sequence Error Register */
AT91_REG EMAC_ALE; /* Alignment Error Register */
AT91_REG EMAC_DTE; /* Deferred Transmission Frame Register */
AT91_REG EMAC_LCOL; /* Late Collision Register */
AT91_REG EMAC_ECOL; /* Excessive Collision Register */
AT91_REG EMAC_CSE; /* Carrier Sense Error Register */
AT91_REG EMAC_TUE; /* Transmit Underrun Error Register */
AT91_REG EMAC_CDE; /* Code Error Register */
AT91_REG EMAC_ELR; /* Excessive Length Error Register */
AT91_REG EMAC_RJB; /* Receive Jabber Register */
AT91_REG EMAC_USF; /* Undersize Frame Register */
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